Apple Computer Inc.s latest professional desktops have sparked a heated debate in the Mac community. At the center of the controversy: Are the dual Motorola PowerPC G4 processors within each Power Mac able to draw on the architectural enhancements being touted by Apple?
Among a raft of other architectural enhancements, the new Power Macs, announced last week in dual 867MHz, 1GHz and 1.25GHz configurations, are the first to include DDR memory. Apples Web site says that this change boosts throughput between memory and the system controller to 2.7GB/sec, increasing "total system performance."
Bare Feats, a Web site that speed-tests Apple hardware, pitted the new dual 1GHz model against the companys previous top-of-the-line offering, an SDRAM-based dual-1GHz system that Apple unveiled in January.
Rob Art Morgan, proprietor of Bare Feats, concluded that the new DDR Power Mac has no apparent performance advantage. Morgan told eWEEK that the tests he ran take advantage of the CPU, memory and other system components in varying degrees, depicting typical consumer and professional use.
Bare Feats also posted a variety of theories on where the bottleneck exists. The most plausible explanation, Morgan says, is that the two G4 processors share a 1.3GB/sec connection to the system controller, and that if the new Power Macs were to use Motorolas latest 7470 version of the G4 instead of the 7455 that shipped in the earlier SDRAM generation of Power Macs, the full advantages of DDR memory could be realized.
Cupertino, Calif.-based Apple declined to specify the generation of processor in the 867MHz and 1GHz systems, shipping now, or the 1.25GHz model, which is due to arrive in September.
One longtime Apple developer told eWEEK he agrees with Bare Feats conclusions. "The fact remains that the G4s share a 1.3GB/sec connection to the system controller, so any theoretical boost to 2.7GB/sec bandwidth is mostly theoretical," he said. "Their latest line of rather deceptive marketing has just kind of pushed me over the top."
He also noted that typical PC chip sets use a number of independent buses for each CPU, to maintain high bandwidth. "In addition," he said, "heavily integrated chip sets from SiS and Nvidia have separate connects for each subsystem, so theyre not all fighting for the same bandwidth."