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By Mark Hachman  |  Posted 2004-06-25 Email Print this article Print
 
 
 
 
 
 
 


Since then, IBM has remained mum on the issue, according to analysts who follow the semiconductor manufacturing industry. Confidential defect-density reports shown to Risto Puhakka, vice president of VLSI Research Corp. in Santa Clara, Calif., has led him to believe that "IBMs problems are behind them," Puhakka said. "Weve talked a couple times since but havent disclosed it further," Puhakka said. "The problem is that to nail it down youd have to go pretty deep on them."
In some sense, aggressively ramping process technologies is out of the hands of an IBM or an Intel; its the responsibility of the manufacturers of lithography equipment. At an International Electronics Forum meeting in the Czech Republic in May, IBM executives seemed to pooh-pooh the idea that aggressively ramping process technology nodes was the secret to getting ahead in the chip industry.
"The real road maps going forward are going to be innovation road maps, not lithography road maps," Bernie Meyerson, IBMs chief technology officer, said, as reported by EE Times. "Its not just lithography that is driving progress." IBMs 90-nm process technology combines silicon-on-insulator, copper interconnects and "strained silicon," which lines up silicon atoms with a substrate whose atoms are placed farther apart. In the strained silicon, electrons experience less resistance and flow up to 70 percent faster, according to IBM. All three methods are designed to decrease electrical resistance within the chip and allow them to run faster. IBM has yet to combine these with low-k dielectrics, designed to reduce resistance further. The problem low-k introduces is one of stability, Puhakka said. "Low-k dielectric presents a major integration issue in terms of the softness of that material," he said. "All that upside becomes much more difficult. … SOI doesnt affect [the structure] that much; copper has some effect on it, placing the two materials side-by-side in that structure."
"What I really expect is for the recipe to become more complex, and for them to talk about [adding] high-k metal gates," designed to electrically separate the source from the drain in an electrical transistor, Puhakka said. High-k gates are most often used to minimize leakage current, a critical element in developing chips for mobile applications. Norman Rohrer, the chief architect of the PowerPC 970FX told eWEEK.com that the company is trying to massage its process technologies to push the current G5 chip into notebooks. For its part, Intel spokesman Manny Vara challenged the idea that the scaling of process technologies from 130nm to 90nm and beyond is dead. "They [IBM] have been talking a bit lately about CMOS not scaling moving forward and how that can slow Moores Law, etc.," he said from the companys Santa Clara headquarters. "We do not agree with their take. We agree that it is more difficult to continue to scale as you move to smaller sizes, but thats no different from what weve faced in the past." Next Page: IBMs unique niche.



 
 
 
 
 
 
 
 
 
 
 

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