Multi-core Processors

By John Busch  |  Posted 2009-09-29 Print this article Print

Multi-core processors

Multi-core processors place many processors and shared caches on a single chip, providing very high potential performance throughput for workloads with thread-level parallelism. To fully realize the benefits of advanced multi-core processors, applications and operating environments need to have many parallel threads with very fast switching between them. They also need to support memory affinity and have granular concurrency control to prevent serialization effects.

Flash memory

Flash memory is a non-volatile computer memory that can be electrically erased and reprogrammed. Flash memory has many promising characteristics but also many idiosyncrasies. Flash memory offers access times that are one hundred times faster than those of hard disk drives (HDDs) and requires much less space and power than HDDs. It consumes only 1/100th the power of DRAM and can be packed much more densely-providing much higher capacities than DRAM.


Flash memory is also cheaper than DRAM and is persistent when written, whereas DRAM loses its content when the power is turned off. Flash memory can be organized into modules of different capacities, form factors and physical and programmatic interfaces.


However, flash memory access times are much slower than DRAM and flash memory chips have write access behavior that is very different than their read access behavior. Flash memory writes can only be done in large blocks (~128KB) and, before writing, the region needs to be erased. Also, flash memory has limits on how many times it can be erased. As a result, small writes need to be buffered and combined into large blocks before writing (write coalescing), and block writes need to be spread uniformly across the total flash memory subsystem to maximize the effective lifetime (wear leveling).


The latency, bandwidth, capacity and persistence benefits of flash memory are compelling. However, incorporating flash memory into system architectures requires specific design and optimization-starting at the application layer, throughout the operating environment and down to the physical machine organization.


Dr. John Busch is President, CEO and co-founder of Schooner Information Technology. John has more than 25 years of industry experience. Prior to Schooner, he was research director of computer system architecture and analysis at Sun Microsystems laboratories from 1999 through 2006. In this role, he led research explorations in chip multiprocessing, advanced multi-tier clustered systems for deployment of Internet-based services, and advanced HPC systems. He received the top President's Award for Innovation at Sun, and oversaw many division technology transfers. Prior to Sun, he was VP of engineering and business partnerships with Diba, Inc., and was general manager of the Diba division after Sun acquired Diba in 1997. From 1989 to 1994, he was co-founder and CTO/VP of engineering of Clarity Software, and led creation of advanced multimedia composition and communication products for Sun, HP and IBM computer systems. From 1976 to 1993, he led many successful R&D programs at Hewlett-Packard in Computer Systems Research and Development. John holds a Ph.D. in Computer Systems Architecture from UCLA, a Master's degree in mathematics from UCLA, a Master's degree in computer science from Stanford University, and attended the Sloan Program at Stanford University. He can be reached at

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