IBM Produces First Prototype of 32-nm Embedded SOI Chip

 
 
By Chris Preimesberger  |  Posted 2009-09-18 Print this article Print
 
 
 
 
 
 
 

UPDATED: The 32-nanometer, silicon-on-insulator chip, used mostly in embedded applications, is designed for products ranging from servers to consumer electronics. SOI protects the transistors on the chip with a blanket of insulation that reduces electrical leakage, saving power and allowing current to flow through the circuit more efficiently, IBM said.

IBM said Sept. 18 that it has developed a prototype of what it claims is the semiconductor industry's smallest, densest and fastest on-chip dynamic memory device.

The 32-nanometer, silicon-on-insulator (SOI) chip, used mostly in embedded applications, is designed for products ranging from servers to consumer electronics.

SOI protects the transistors on the chip with a blanket of insulation that reduces electrical leakage, saving power and allowing current to flow through the circuit more efficiently, IBM said.

IBM's test SOI chip with an embedded dynamic random access memory (eDRAM) uses the industry's smallest memory cell. IBM also claims that the new chip will provide better areal density, speed and capacity than conventional on-chip static random access memory (SRAM) that already has been announced in 32-nm and 22-nm form factors.

IBM itself is developing those other smaller sizes. Big Blue and its joint development partners Advanced Micro Devices, Freescale, STMicroelectronics, Toshiba and the College of Nanoscale Science and Engineering said last month they have developed the first working SRAM cell implemented in a 22-nm manufacturing process. The cell was built at CNSE's 300-mm research facility in Albany, N.Y.

The SRAM is a basic building block of both high-performance memory and complex logic circuits such as microprocessors. The IBM 22-nm SRAM cell utilizes a conventional six-transistor design and has an area of 0.1 square microns, the company said.

IBM said its SOI technology can provide up to a 30 percent chip performance improvement and 40 percent power reduction compared with standard bulk silicon technology.

"This competes with SRAM on the chip, which accounts for about 50 percent of the die area of all high-performance processor chips," Jim Handy of Objective Analysis told eWEEK.
 
"By moving from SRAM [today's norm] to DRAM, these chips should shrink a good bit. Take that 50 percent and lop off three-quarters of it [since they say it's four times as dense as 32-nm SRAM], and you will get a 37 percent die size reduction, which chip makers can take straight to the bank.
 
"But it only makes sense to use this technology if the rest of the chip already needs to use SOI.  SOI is a very expensive process," Handy said.

Intel, the world's largest chip maker, is far beyond 32nm prototypes, with 32nm wafers moving through the factory floor for planned Q4 revenue production, Intel spokeswoman Megan Langer told eWEEK in an email. "The 32nm prototype, our test chip, was shown in two years ago at the Intel developer forum.

"We are still the only company showing working demonstrations vs. talking about the technology in a paper."

As for eDRAM, Langer said, it's a technology Intel and other manufacturers have  intentionally chosen not to implement due to the "massive cost of implementation and need for more process steps and hence much higher cost than SRAMs."

"Intel is not using eDRAMs in any of its CPU logic or SoC technologies and has not announced any plans to do so at this time," Langer said. "For now, we have found other ways to reduce power (like our high-k metal gates, for example) and eDRAM hasn't proven to be worth the additional cost involved (for manufacturers and ultimately end users)."

Editor's note: This story has been updated to correct previous information about Intel's 32-nm chip development and add comment from Intel.


 
 
 
 
Chris Preimesberger Chris Preimesberger was named Editor-in-Chief of Features & Analysis at eWEEK in November 2011. Previously he served eWEEK as Senior Writer, covering a range of IT sectors that include data center systems, cloud computing, storage, virtualization, green IT, e-discovery and IT governance. His blog, Storage Station, is considered a go-to information source. Chris won a national Folio Award for magazine writing in November 2011 for a cover story on Salesforce.com and CEO-founder Marc Benioff, and he has served as a judge for the SIIA Codie Awards since 2005. In previous IT journalism, Chris was a founding editor of both IT Manager's Journal and DevX.com and was managing editor of Software Development magazine. His diverse resume also includes: sportswriter for the Los Angeles Daily News, covering NCAA and NBA basketball, television critic for the Palo Alto Times Tribune, and Sports Information Director at Stanford University. He has served as a correspondent for The Associated Press, covering Stanford and NCAA tournament basketball, since 1983. He has covered a number of major events, including the 1984 Democratic National Convention, a Presidential press conference at the White House in 1993, the Emmy Awards (three times), two Rose Bowls, the Fiesta Bowl, several NCAA men's and women's basketball tournaments, a Formula One Grand Prix auto race, a heavyweight boxing championship bout (Ali vs. Spinks, 1978), and the 1985 Super Bowl. A 1975 graduate of Pepperdine University in Malibu, Calif., Chris has won more than a dozen regional and national awards for his work. He and his wife, Rebecca, have four children and reside in Redwood City, Calif.Follow on Twitter: editingwhiz
 
 
 
 
 
 
 

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