Intel, Micron Unveil 25-Nm NAND Flash Chip

 
 
By Chris Preimesberger  |  Posted 2010-02-01 Email Print this article Print
 
 
 
 
 
 
 

The new 25-nanometer, 2-bit-per-cell chip from Intel and Micron Technology can hold 8GB of data storage, more than 10 times the 700MB capacity of a standard CD. The chip measures a mere 167 square millimeters, making it small enough to fit through the hole in the middle of a CD.

Intel and Micron Technology set the NAND flash capacity bar a little higher and the chip size threshold a little lower Feb. 1 with the introduction of the world's first 25-nanometer solid-state processor.

The 25-nm, 2-bit-per-cell chip can hold 8GB of digital capacity, more than 10 times the 700MB capacity of a standard CD. The chip measures a mere 167 square millimeters-small enough to fit through the hole in the middle of a CD.

"This is not only the smallest NAND lithography in the world, it is the smallest silicon manufacturing technology in the world," Intel Marketing Director Troy Winslow told eWEEK on a conference call. "This is now the largest-capacity multilevel cell device on the market, at 8GB. We were the first on 34 nm, now we're the first on 25 nm."

The smaller size allows multiple 8GB chips to be packaged more economically to increase storage capacity. The new 25-nm 8GB device reduces chip count by 50 percent compared with previous process generations, allowing for smaller yet higher-density designs and greater cost efficiency, Winslow said.

For example, a 256GB solid-state drive now only needs 32 of these devices, versus 64 previously, Winslow said, while a 32GB smartphone needs only four and a 16GB flash card requires only two.

NAND flash memory, used in consumer devices such as smartphones, digital cameras, and personal music and media players, stores data and retains the information even when the power is turned off. NAND flash also is gaining popularity for use in high-performance solid-state drives for servers and storage arrays.

IM Flash Technologies, Intel and Micron's NAND flash joint venture, continues to cram more capacity into tinier pieces of silicon about every six to eight months. IMFT debuted its 34-nm, 3-bit-per-cell NAND flash chip in August 2009.

The 25-nm, 8GB chip is sampling now and is expected to enter mass production in the second quarter, Winslow said.

 
 
 
 
Chris Preimesberger Chris Preimesberger was named Editor-in-Chief of Features & Analysis at eWEEK in November 2011. Previously he served eWEEK as Senior Writer, covering a range of IT sectors that include data center systems, cloud computing, storage, virtualization, green IT, e-discovery and IT governance. His blog, Storage Station, is considered a go-to information source. Chris won a national Folio Award for magazine writing in November 2011 for a cover story on Salesforce.com and CEO-founder Marc Benioff, and he has served as a judge for the SIIA Codie Awards since 2005. In previous IT journalism, Chris was a founding editor of both IT Manager's Journal and DevX.com and was managing editor of Software Development magazine. His diverse resume also includes: sportswriter for the Los Angeles Daily News, covering NCAA and NBA basketball, television critic for the Palo Alto Times Tribune, and Sports Information Director at Stanford University. He has served as a correspondent for The Associated Press, covering Stanford and NCAA tournament basketball, since 1983. He has covered a number of major events, including the 1984 Democratic National Convention, a Presidential press conference at the White House in 1993, the Emmy Awards (three times), two Rose Bowls, the Fiesta Bowl, several NCAA men's and women's basketball tournaments, a Formula One Grand Prix auto race, a heavyweight boxing championship bout (Ali vs. Spinks, 1978), and the 1985 Super Bowl. A 1975 graduate of Pepperdine University in Malibu, Calif., Chris has won more than a dozen regional and national awards for his work. He and his wife, Rebecca, have four children and reside in Redwood City, Calif.Follow on Twitter: editingwhiz
 
 
 
 
 
 
 

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