Intel, Numonyx Reveal Stacking Breakthrough in PCM Research

 
 
By Chris Preimesberger  |  Posted 2009-10-28 Email Print this article Print
 
 
 
 
 
 
 

Phase change memory is a relatively new type of nonvolatile memory chip that combines many of the benefits of current memory types, such as NAND flash, NOR flash and hard disk drives. Research engineers say they have found a way to stack up 64MB single-layer PCM arrays within a single die into what Intel and Numonyx describe as a true cross-point array containing both memory and a switch.

Intel and its solid-state processor research affiliate, Numonyx, on Oct. 28 revealed what they described as a "key breakthrough" in their continuing research on phase-change memory, or PCM.

Numonyx Layered PCM chipPCM is a relatively new type of nonvolatile memory chip that combines many of the benefits of current memory types, such as NAND flash, NOR flash and hard disk drives.

In brief, the companies said research engineers have found a way to stack up 64MB single-layer PCM arrays within a single die into what Intel and Numonyx describe as a true "cross-point array" containing both memory and a switch for interconnection purposes.

The result is a vertically integrated memory cell called a PCMS (phase-change memory and switch). A PCMS consists of one PCM element layered with an OTS (Ovonic Threshold Switch).

This promises substantial gains in scalability, performance and power savings that are projected to be magnitudes better than what is possible in current solid-state and spinning disk storage, said Al Fazio, Intel fellow and director of memory technology development.

A PRAM (phase-change memory) chip is nonvolatile memory that is works equally well for executing code and storing large amounts of data, giving it capabilities of both flash memory and DRAM (dynamic RAM). This means PCM can execute code with performance, store larger amounts of memory and sustain millions of read/write cycles.

Stacked up, these chips have the potential for read/write speed and storage capability far beyond anything yet seen in electronics.

The key descriptor here, however, is the word "potential." Fazio and Numonyx Senior Technology Fellow Greg Atwood explained that such a multilayer PCM processor has not actually been tested: Only the single-layer 64MB chip has been tested, and the stackability attributes have been identified and designed.

"Our testing has involved single-layer 64MB PCM array on top of a CMOS. We've tested the array for reliability and distributional properties," Fazio told eWEEK during a conference call. "The multiple-layer version-whether it's two or four or multiple layers stacked up on top of each other-is yet to be done. But this is the first and most significant milestone, which is the basic stacking in a large, multimegabit array."

A whitepaper with details on the multilayer PCM breakthrough-and more information about the performance of a stacked PCM array-will be made available in December at the International Electron Devices Meeting in Baltimore, Fazio said.

The breakthrough, Fazio said, was producing the building blocks and demonstrating the PCM chip at a single layer.

"The first layer is the hardest layer," Atwood told eWEEK.

Overall, the results of more than six years of PCM research are extremely promising, Atwood said.

"The results show the potential for higher density, scalable arrays and NAND-like usage models for PCM products in the future," he said. "This is important as traditional flash memory technologies face certain physical limits and reliability issues, yet demand for memory continues to rise in everything from mobile phones to data centers."



 
 
 
 
Chris Preimesberger Chris Preimesberger was named Editor-in-Chief of Features & Analysis at eWEEK in November 2011. Previously he served eWEEK as Senior Writer, covering a range of IT sectors that include data center systems, cloud computing, storage, virtualization, green IT, e-discovery and IT governance. His blog, Storage Station, is considered a go-to information source. Chris won a national Folio Award for magazine writing in November 2011 for a cover story on Salesforce.com and CEO-founder Marc Benioff, and he has served as a judge for the SIIA Codie Awards since 2005. In previous IT journalism, Chris was a founding editor of both IT Manager's Journal and DevX.com and was managing editor of Software Development magazine. His diverse resume also includes: sportswriter for the Los Angeles Daily News, covering NCAA and NBA basketball, television critic for the Palo Alto Times Tribune, and Sports Information Director at Stanford University. He has served as a correspondent for The Associated Press, covering Stanford and NCAA tournament basketball, since 1983. He has covered a number of major events, including the 1984 Democratic National Convention, a Presidential press conference at the White House in 1993, the Emmy Awards (three times), two Rose Bowls, the Fiesta Bowl, several NCAA men's and women's basketball tournaments, a Formula One Grand Prix auto race, a heavyweight boxing championship bout (Ali vs. Spinks, 1978), and the 1985 Super Bowl. A 1975 graduate of Pepperdine University in Malibu, Calif., Chris has won more than a dozen regional and national awards for his work. He and his wife, Rebecca, have four children and reside in Redwood City, Calif.Follow on Twitter: editingwhiz
 
 
 
 
 
 
 

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