Samsung Ships Its First 20Nm-Class NAND Flash Memory

 
 
By Chris Preimesberger  |  Posted 2010-04-19 Email Print this article Print
 
 
 
 
 
 
 

Thanks to its latest fabrication methodology, Samsung's high-density, 32G-bit, 8GB MLC NAND puts the company in the lead as a producer of solid-state memory processors for smartphones, high-end IT applications and high-performance memory cards.

Several companies-including Intel/Micron and Toshiba-have been talking about it, but Samsung Electronics April 19 was the first to announce that it is now producing 20-nanometer-class NAND flash chips for use in memory cards made for handheld devices and embedded deployments.

Samsung, however, would not reveal to eWEEK the actual size of the node that it is shipping, preferring to call it "20nm-class" NAND flash. The actual size of the nodes could be anywhere from 20nm to 29nm in size.

In that vein, Micron announced on Feb. 1 that it will begin mass producing 25nm NAND flash chips in Q2.

Thanks to this latest fabrication methodology, Samsung's high-density 32G-bit, 8GB MLC (multilevel cell) NAND puts the company in a good place at this time as a producer of solid-state memory processors for smartphones, high-end IT applications and high-performance memory cards.

Samsung is advancing its fab capabilities quickly. Only one year ago, the company was the first to move to the 30-nm fabrication process.

NAND flash manufacturers often leapfrog each other as smaller, more efficient chip fabrication processes come into use.

Samsung Memory Division President Soo-In Cho said the write performance of the new 20-nm SD (secure disk) card is 30 percent faster than the 30-nm-class NAND and it delivers a speed-class rating of 10 (read speed of 20MB per second, write speed of 10MB per second).

Increasingly minuscule flash chips provide advantages for both manufacturers and users. The smaller flash memory processors are, the more flash chips can fit on a single wafer in the fabrication process, which lowers the cost per chip.

A 20-nm chip-as compared with, say, a 32-nm or 45-nm chip being produced today-also allows a device to be loaded with more memory capacity within the same physical space boundaries, which invariably leads to marked performance improvements.

A statement from Micron

Kevin Kilbuck, director of NAND marketing at Micron, emailed the following statement to eWEEK about Samsung's announcement on April 19:

"As you know, we have entered volume production on our 25nm NAND, and we believe we are the first to do so on any "20nm class" process node.

"While there may be differences in terms of the process technology itself, they are fundamentally all "20nm class" NAND flash technologies. Therefore the key differentiator is when volume production commences.  

"Another good measure of the effectiveness of the new technology is density and package size. For example, Micron's 25nm 64Gb (8GB) MLC NAND fits in an industry standard 12mm by 20mm TSOP.

"Finally it's important to look at whether the new technology can be sold to customers in 'raw' NAND form, or whether it needs to be shipped behind a controller, e.g. in a flash card or a USB drive. Micron's 25nm technology has been qualified in raw NAND form by numerous customers serving a wide variety of applications."

 
 
 
 
Chris Preimesberger Chris Preimesberger was named Editor-in-Chief of Features & Analysis at eWEEK in November 2011. Previously he served eWEEK as Senior Writer, covering a range of IT sectors that include data center systems, cloud computing, storage, virtualization, green IT, e-discovery and IT governance. His blog, Storage Station, is considered a go-to information source. Chris won a national Folio Award for magazine writing in November 2011 for a cover story on Salesforce.com and CEO-founder Marc Benioff, and he has served as a judge for the SIIA Codie Awards since 2005. In previous IT journalism, Chris was a founding editor of both IT Manager's Journal and DevX.com and was managing editor of Software Development magazine. His diverse resume also includes: sportswriter for the Los Angeles Daily News, covering NCAA and NBA basketball, television critic for the Palo Alto Times Tribune, and Sports Information Director at Stanford University. He has served as a correspondent for The Associated Press, covering Stanford and NCAA tournament basketball, since 1983. He has covered a number of major events, including the 1984 Democratic National Convention, a Presidential press conference at the White House in 1993, the Emmy Awards (three times), two Rose Bowls, the Fiesta Bowl, several NCAA men's and women's basketball tournaments, a Formula One Grand Prix auto race, a heavyweight boxing championship bout (Ali vs. Spinks, 1978), and the 1985 Super Bowl. A 1975 graduate of Pepperdine University in Malibu, Calif., Chris has won more than a dozen regional and national awards for his work. He and his wife, Rebecca, have four children and reside in Redwood City, Calif.Follow on Twitter: editingwhiz
 
 
 
 
 
 
 

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