AMD, IBM Tout Chip Performance Gains

 
 
By John G. Spooner  |  Posted 2005-12-06 Email Print this article Print
 
 
 
 
 
 
 

The two chip makers say that together they've developed a recipe that can boost performance of their chips at the 65-nanometer level and below.

Advanced Micro Devices Inc. and IBM are intentionally introducing strain into their chip-making partnership. The two companies on Tuesday detailed some of their work in developing new chip manufacturing techniques that will boost transistor performance, yet help limit power consumption, in chips with circuits knitted together at the 65-nanometer level and below. The revelations, which include using strain, a technique that repositions the internal structures of a chip to boost its performance, were made in papers presented at the International Electron Devices Meeting in Washington.
While delivering ever-greater performance is the lifeblood of a chip maker, power is becoming increasingly more important as well.
Consumers and businesses are beginning to demand more power-efficient processors for notebooks as well as servers, while at the same time chip makers themselves are seeking performance gains by packaging two or more processor cores inside each chip. AMD, IBM and Intel Corp. all now produce dual-core chips, or chips which have two processor cores built in. However, the chips have been limited to high-end desktops and servers thus far.
Moving multicore processors, which promise performance bumps by throwing more than one processor at a computing job, into notebooks and mainstream desktops will require 65-nanometer production, most experts say. Click here to read about AMDs plans for quad-core chips. To that end, AMD and IBM said in their joint statement that they have combined several chip-making techniques into a recipe that offers a 40 percent increase in transistor performance, when compared with like chips made without stress technology, but that at the same time maintains control over power consumption and heat dissipation. The companies said they have combined Silicon Germanium, Dual Stress Liner and Stress Memorization and placed them on top of Silicon-On-Insulator wafers. The net result of this cocktail allows chips to herd electrons efficiently, which boosts performance and cuts down on wasted electricity. "Our joint work on developing advanced process technologies continues to ensure that we can create and provide the highest-performance, lowest-power processors on the market," Nick Kepler, vice president of logic technology development at AMD, said in a statement. AMD has begun pilot production at 65 nanometers at its recently opened Fab 36 plant in Dresden, Germany. The chip maker expects to begin full 65-nanometer production in the latter half of 2006, Kepler said in a recent interview with Ziff Davis Internet. "Our progress on 65-nanometer technology is going very well," Kepler said in that interview. "Weve gotten very good results on the technology at this stage." IBM of Armonk, N.Y., has also said it plans to convert its chip plant in East Fishkill, N.Y., from 90-nanometer production to 65-nanometer production over time. IBM has already begun prototyping its 65-nanometer process while it moves equipment into a special annex at the Fishkill plant thats designed to produce both 65-nanometer and 45-nanometer chips. A company executive told Ziff Davis Internet earlier this year that IBM is aiming to make the 65-nanometer transition in 2006. However, the company has yet to say exactly when it will get started with its 65-nanometer chip production. Read more here about Intels two 65-nanometer manufacturing processes. Intel, for its part, has already been shipping 65-nanometer chips, including Presler, a dual-core desktop processor, for revenue. The Santa Clara, Calif., company, which is expected to introduce dual-core, 65-nanometer processors in desktops and notebooks in January, is already producing 65-nanometer chips at two plants and plans to add two more before the end of 2006, it has said. Chip manufacturers generally move to new and successively smaller manufacturing processes every two years. These shifts, which can cost billions and take years of development, allow them to produce chips with greater numbers of transistors, but still make the chips smaller by packing those features more tightly together. Check out eWEEK.coms for the latest news in desktop and notebook computing.
 
 
 
 
John G. Spooner John G. Spooner, a senior writer for eWeek, chronicles the PC industry, in addition to covering semiconductors and, on occasion, automotive technology. Prior to joining eWeek in 2005, Mr. Spooner spent more than four years as a staff writer for CNET News.com, where he covered computer hardware. He has also worked as a staff writer for ZDNET News.
 
 
 
 
 
 
 

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