AMD Invites Users, Developers to Set Their Own 64-Bit Pace

 
 
By Peter Coffee  |  Posted 2003-04-22 Email Print this article Print
 
 
 
 
 
 
 

The launch of Opteron puts the spotlight on the almost trivial difference between AMD's and Intel's strategies, but the companies are really just placing different bets in the same casino of complex and costly designs.

Its not an easy time to be either Intel or AMD. The launch of puts the spotlight on the almost trivial difference between their strategies, but the companies are really just placing different bets in the same casino of complex and costly designs. Its a gaming hall that both of these chip makers were forced to enter by the relentless pressures of semiconductor fabrication progress. Given the option, we wonder if both companies would rather just spend a quiet evening at home knitting memory chips and mobile processors. But that choice is not on the table, at least not at the margins that both companies need to support their present business models and future growth ambitions. Instead, both companies hope that the mass-market economics of high-volume processor production will draw resource-limited server manufacturers—and cost-conscious enterprise buyers—into their 64-bit game. Server processing power is clearly a buyers market. Intel has been almost embarrassed by its own success in continuing to squeeze higher clock rates, if not proportional performance gains, from the aging Pentium architecture and its Xeon server-optimized configurations.
The question, though, is how much opportunity remains to analyze an ever-more-rapid flow of Pentium-style instructions, on the fly, in search of opportunities to transform them into entwined (but not entangled) streams of concurrent operations. Two different answers to that question define the difference between Itanium and Opteron as the next logical step for server CPUs.
Intel is betting that on-chip instruction-scheduling hardware, which emerged on x86 chips in the late 1990s to inject new life into 1980s code, is nearing its limit—that added cost, in terms of complexity of design and share of on-chip resources, will soon exceed increased contribution. Each successive generation of Pentium processor has shown a smaller percentage increase in the number of instructions per clock cycle, with the Pentium 4 actually suffering a decline; thread-level parallelism, such as Intels Hyperthreading, offers perhaps another few tens of percentage points of performance gain, but this approach increases the workload at the edge of the chip where congestion is already a problem.


 
 
 
 
Peter Coffee is Director of Platform Research at salesforce.com, where he serves as a liaison with the developer community to define the opportunity and clarify developers' technical requirements on the company's evolving Apex Platform. Peter previously spent 18 years with eWEEK (formerly PC Week), the national news magazine of enterprise technology practice, where he reviewed software development tools and methods and wrote regular columns on emerging technologies and professional community issues.Before he began writing full-time in 1989, Peter spent eleven years in technical and management positions at Exxon and The Aerospace Corporation, including management of the latter company's first desktop computing planning team and applied research in applications of artificial intelligence techniques. He holds an engineering degree from MIT and an MBA from Pepperdine University, he has held teaching appointments in computer science, business analytics and information systems management at Pepperdine, UCLA, and Chapman College.
 
 
 
 
 
 
 

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