Intel Shifts to Next-Gen Strained Silicon

 
 
By Mark Hachman  |  Posted 2004-08-30 Email Print this article Print
 
 
 
 
 
 
 

Intel Corp. will shift to a second-generation strained-silicon technique within its forthcoming 65-nanometer process technology. (ExtremeTech)

Intel Corp. will shift to a second-generation strained-silicon technique within its forthcoming 65-nanometer process technology, the company will announce on Monday. Intel has been able to produce 65-nm SRAM cells using the new technology, executives said, concentrating on minimizing the wasted power produced by the finished chips. The process also adds a metal layer, increasing the total to eight. The shift to new process technologies, as always, is a tricky one. Intel, IBM, and foundry Taiwan Semiconductor Manufacturing Co. have all suffered missteps on their shift to the new 90-nm process. Intel executives said theyve managed to fabricate a 65-nm cell with over half a billion transistors, helping Intels manufacturing teams inch forward on these "practice" designs before a push into logic production begins some time next year. Intel officials have said that the "crossover" between the current 90-nm designs and the 65-nm chips will occur sometime in 2006.
Every semiconductor company either designs its own manufacturing process or uses a foundry, like IBM or TSMC, to design one for them. Aggressively shifting to new process technologies is seen as critical for the latest chip designs like microprocessors or graphics chips.
Supporting components, such as a chipset, are often produced on older, more mature 130-nm (0.13-micron) or 180-nm processes that have already paid for themselves years ago producing then cutting-edge parts. The labels attached to each generation – 130-nm, for example – are actually legacy terms attached to each generation. In reality, each chip manufacturer designs transistors of arbitrary length; Intels new transistors are actually 35 nanometers long. Facilitating the shift is also critical – being first to market with a new process is of little use if the process itself is unworkable. Mark Bohr, a senior fellow at Intel and director of process integration, said that the 65-nm transition should actually be smoother than prior generations. "I would expect the transition may be slightly easier than in the past," he said. "We have a couple of brand new materials, but weve done strained silicon…in 90-nanometers for the second time." The company took a "little more risk" on the 90-nm generation, since it was the first time strained silicon was introduced.
Strained silicon occurs when the gaps between the electrical substrate are widened, prompting the silicon atoms to widen as well. This lowers the electrical resistance, causing electrons to require fewer hops between atoms. Intels second-generation strained silicon delivers 30 percent better performance than non-strained silicon or a fifteen percent improvement over the prior generation, Bohr said. Intels second-generation process shifted to a PMOS process, versus the NMOS process it used before. Many companies are working on PMOS, Bohr claimed, but none have perfected PMOS. Intel and other chip companies measure success by the ratio between ION, the drive current, and IOFF, the leakage current. The formula is simple: maximize the drive current to increase speed, while minimize the leakage current to minimize the power used by the chip. Intels second-generation strained silicon can be used to provide a 4X reduction in leakage current. In theory, chips with more finely draw transistors can run faster and consume less power than older components. Intels 65-nm chips could be run at 0.7 volts or perhaps less, Bohr said. Intels 35-nm process will also be the first to use "sleep transistors", first introduced in academic papers on 2001 and 2002. Sleep transistors work like duct tape on a leaky pipe. Minimizing the capacitance needed for a circuit to flow through a transistor is desirable; Intel cut its capacitance by twenty percent by maintaining the same 1.2-nm gate oxide thickness but cutting its transistor length. But the same capacitance that can facilitate flowing current is also like a porous plug; the lower the capacitance, the more likely that current will slowly seep out over time. Sleep transistors will be added to blocks within memory arrays, largely minimizing the power reduction, Bohr said. The additional transistors will likely add just one percent to the overall transistor count, he said. Intels 65-nm manufacturing lines will be brought up at the "D1D" fab in Hillsboro, Ore., followed by Fab 12 in Arizona and Fab 24 in Ireland, Bohr said. Check out eWEEK.coms Desktop & Notebook Center at http://desktop.eweek.com for the latest news in desktop and notebook computing.
 
 
 
 
 
 
 
 
 
 
 

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