CPU Power Push

 
 
By Peter Coffee  |  Posted 2002-10-28 Email Print this article Print
 
 
 
 
 
 
 

New chips leave device and app designers, IT architects looking to find ways to drink it all in.

In the debut of desktop computing, general-purpose microprocessors opened the door to affordable single-user systems. The limited power of those early CPUs meant that almost every advance in chip speed—or expansion of address space—yielded substantial improvement in visible and relevant performance. Every year, announcements at the Microprocessor Forum told the industry what new chips would propel the next wave of PC and server sales.

At this years Microprocessor Forum, in San Jose, Calif., conference founder Michael Slater ruefully observed that two decades of Moores Law progress have put the microchip industry, perversely, in the position of having more power to sell than most PC buyers can use. "Raw compute horsepower," said Slater in remarks at the end of the forums first day, "is the easy part. Yes, faster processors are enabling components—but the computer science of next-generation usability is years behind the hardware."

The result, Slater warned, is that "there will not be volume demand at the leading edge"—at least, not the kind of demand that historically greeted landmark microchips, such as Intel Corp.s 386, 486 and Pentium, with hordes of eager buyers. The resulting challenge for microprocessor designers, he said, will increasingly be to focus on "solutions, not horsepower."

Slaters comments suggest a shift of power—from technology providers to technology buyers—in dictating the direction and pace of future hardware evolution. The alternative paths available to enterprise IT buyers were displayed in forum presentations from key players Intel; Advanced Micro Devices Inc.; Motorola Inc.; and Centaur Technology, a subsidiary of Via Technologies Inc.—each company staking out a different corner of the microchip arena.

Intel, with the resources of what Slater called "a capital-rich manufacturing machine," came to San Jose with an array of elaborate offerings.

For mobile applications, Intel stated a new design goal of maximizing performance within a defined power envelope. This is in contrast to the companys former approach of producing mobile processors as, essentially, trickle-down byproducts of the manufacturing-process improvements made to each successive generation of its peak-performance designs.

When power consumption moves to the head of the list of design criteria, interesting opportunities arise.

For example, a circuit element performing a logical AND operation will produce a "logical low" output if either of its two inputs is low, and a conventional chip design would not make any special effort to hold both inputs low in the most common case since there is no difference in the logical effect.

There is, however, a factor-of-5 difference in the leakage current, as described by Mooly Eden, general manager of Intels Israel Design Center. When the Level 2 cache for Intels forthcoming Banias family was designed with this in mind, Eden said, more than a full watt of power consumption was saved. (For more on Banias, see story.)

This illustrates the opportunities available to Intel, and therefore to portable PC buyers, to pursue the goal of "all-day," unplugged computing without giving up the performance of desktop machines.

Intels refocused design will be running the x86 instructions directly, in the same manner as a Pentium III-M or other mobile processors popular in present high-end laptops. This is in contrast to the indirect approach taken by chips such as Transmeta Corp.s Crusoe, which achieves low power consumption by radically simplifying core logic circuits to execute VLIW (very long instruction word) native operations.

Transmeta achieves the x86 compatibility that the market demands by loading, on system startup, an application called Code Morphing that dynamically translates mainstream PC software sequences into Crusoe chip instructions. The rest of the software foundation, including BIOS and other code such as the operating system, then runs on top of that "morphing" layer.

More than just a simple translator, the Transmeta software attempts to make sophisticated trade-offs among speed, consumption of on-chip resources and power demands. It attempts to identify rarely used instructions that can be translated once and then discarded until their next occurrence; it also attempts to cache frequently used sequences in pre- translated form.

For highly repetitive operations, such as image processing or other media-oriented tasks that involve high processor workloads, Transmeta can offer designers an excellent match between form and function. The same approach is also effective in many server roles, which has ironically placed Transmetas portability solution at the heart of several high-density blade server offerings (where cooling is high on the list of challenges).

But "one size does not fit all," asserted Robert Yung, Intels chief technology officer for enterprise processors. Even while the company rethinks its approach to x86 design for mobile markets, it is still moving forward with the completely different instruction set of its IA-64 family in the Itanium 2 and follow-on designs.

Everything about the IA-64 chips is oversized: 328 on-chip storage registers, 50-bit (petabyte-capable) physical address space and probably 10MB of L2 cache before the end of the decade, Yung projected.

Cache already represents 78 percent of the transistor count for the current "McKinley" Itanium core and will grow to 88 percent in the follow-on "Madison" design. This is a signal to enterprise buyers that getting data to and from the processing point is increasingly the dominant problem, rather than expediting computation itself. This is a general imperative that will resonate through every element of enterprise IT design and should drive IT architects toward solutions (such as Web services) that place computation as close as possible to the points where data originates or where users questions arise.

In the opposite corner is Via/ Centaur, represented by forum regular Glenn Henry, president of Centaur Technology. "People really want x86," said Henry in a private session with eWeek Labs. "Theres so much infrastructure of tools, skills and peripherals; if theres an x86 in a space, it will win."

Henrys goal, though, is to channel that momentum toward new applications, "things that hundreds of millions of people want to do," he said.

In Henrys view, that means building appliances such as set-top boxes that dont need cooling fans, or PCs that sell for at most a few hundred dollars—such as the Lindows-based, Centaur-powered Microtel Computer Systems units now selling for as little as $200 at Wal-Mart stores.

"Its not that Pentium 4 is the wrong processor," Henry said, "its just that its volume is inherently limited. Intels parts dont enable new applications."

To prove the point that a compact, fanless, but fully capable PC is deliverable today, Henry showed eWeek Labs a 17-centimeter-square module—"a real board, you can buy this for $130 at Frys," he said—that was built around a Centaur processor and that only draws about 8 watts, "even with every connectivity port known to man. We wanted people to be able to use this for anything," Henry explained.

"Low cost is more important than megahertz," Henry told his forum audience. "Low power is more important than megahertz. Were low cost, low power and fast enough."



 
 
 
 
Peter Coffee is Director of Platform Research at salesforce.com, where he serves as a liaison with the developer community to define the opportunity and clarify developers' technical requirements on the company's evolving Apex Platform. Peter previously spent 18 years with eWEEK (formerly PC Week), the national news magazine of enterprise technology practice, where he reviewed software development tools and methods and wrote regular columns on emerging technologies and professional community issues.Before he began writing full-time in 1989, Peter spent eleven years in technical and management positions at Exxon and The Aerospace Corporation, including management of the latter company's first desktop computing planning team and applied research in applications of artificial intelligence techniques. He holds an engineering degree from MIT and an MBA from Pepperdine University, he has held teaching appointments in computer science, business analytics and information systems management at Pepperdine, UCLA, and Chapman College.
 
 
 
 
 
 
 

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