64 Bits on Desktop

 
 
By Peter Coffee  |  Posted 2002-10-28 Email Print this article Print
 
 
 
 
 
 
 


64 Bits on Desktop

Evidently agreeing with Henry on the primacy of the x86 instruction set is AMD, which appeared at this years forum with the first hard performance numbers for its next-generation x86-compatible chips, which will offer a 64-bit extension of the 32-bit instruction set that debuted in 386-class microprocessors.

Directly rebutting Intels Yung was AMD Vice President and CTO Fred Weber, another forum regular, who said, "We really do believe that one size does fit all—not the same processor but the same instruction set."

Despite years of angels-on-pinheads debate about RISC versus CISC architectures, Weber asserted, the choice of instruction set should be driven by "compatibility, not performance."

Holding up a deck of memory cards, Weber asked the forum audience, "When this is 4GB of RAM, why wouldnt you want a 64-bit system on your desktop?"

Weber added that theres a bonus even for running 32-bit applications in a 64-bit address space.

On a 32-bit platform, he noted, the operating system consumes a substantial fraction of the single 4GB address space that could otherwise be used entirely by the application. "Memory-bound 32-bit applications can have their own full 4GB in our compatibility mode, so they get a one-time memory boost" without being redesigned for the 64-bit platform, he said.

Just as desktop applications quickly took advantage of memory beyond the 1MB limit of the Intel 286 and earlier chips as the 386 became mainstream, its plausible that enterprise applications involving large databases and media-oriented applications involving rich data streams will quickly seize upon the power that Weber describes—as soon as it becomes economical to buy and easy to access with improved platforms and tools.

A major portion of Webers forum presentation was devoted to a discussion of the performance—and especially the scalability to multiprocessor designs—of the nonproprietary HyperTransport protocol to be used by forthcoming AMD chips. In a quadprocessor design, Weber calculated, each processor core could enjoy local memory access at 3.9GB per second, or the four cores could share common memory at 2.8GB per second.

With the high-bandwidth connectivity of AMDs 64-bit Hammer, Weber said, "four-way becomes the norm."

Attendees at past forum conferences must surely have noted the resemblance between Webers talk and presentations by IBM concerning that companys Power4 processor, which also features a bandwidth-rich design thats well-suited to video and other data-intensive applications.

Nor is Intel ignoring this concern: The Itanium 2 is already on its way, according to Intels Yung, into configurations with as many as 512 processors.

Clearly, the interconnection schemes among processors are vying with their internal sophistication for top-of-mind status among prospective buyers.

The fourth corner of the arena is ably defended by Motorolas ColdFire core, a synthesizable chunk of intellectual property thats readily tailored and embedded into both standard and custom products.

New at this years forum was discussion of the forthcoming Version 5, a superscalar design that should typically achieve at least a third more processing per clock cycle than the predecessor Version 4 design.

ColdFires heritage is the 68000 instruction set, probably second only to x86 for ubiquity of programming tools and skills—and a more modern instruction set design from its initial conception.

ColdFire instructions can be 16, 32 or 48 bits in length, but that variety isnt the burden that it was once claimed to be by advocates of uniform-length RISC instructions.

As described by ColdFire Chief Architect Joe Circello, a hardware- resident table produces a vector of operations for each instruction during an early decode stage. This enables, for example, quick determination of whether instructions are interdependent and therefore unsuited to concurrent execution.

Because the ColdFire design avoids any need for hand tuning to different semiconductor process technologies, it offers designers a short time to market with a highly tailored solution, Circello said. "You want a memory management unit? Flip a switch [during design generation, and] it gets synthesized in. Floating-point hardware? Likewise."

Motorolas product groups already take advantage of this flexibility in developing standard parts, as well as offering it for use in custom solutions as enterprises move more advanced technology into the field. With handheld or networked devices distributing intelligence to many points in the manufacturing process and supply chain, such tailored solutions will move higher up on enterprise IT agendas.



 
 
 
 
Peter Coffee is Director of Platform Research at salesforce.com, where he serves as a liaison with the developer community to define the opportunity and clarify developersÔÇÖ technical requirements on the companyÔÇÖs evolving Apex Platform. Peter previously spent 18 years with eWEEK (formerly PC Week), the national news magazine of enterprise technology practice, where he reviewed software development tools and methods and wrote regular columns on emerging technologies and professional community issues.Before he began writing full-time in 1989, Peter spent eleven years in technical and management positions at Exxon and The Aerospace Corporation, including management of the latter companyÔÇÖs first desktop computing planning team and applied research in applications of artificial intelligence techniques. He holds an engineering degree from MIT and an MBA from Pepperdine University, he has held teaching appointments in computer science, business analytics and information systems management at Pepperdine, UCLA, and Chapman College.
 
 
 
 
 
 
 

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