IBM Launches New Features for Power6-Based Servers

 
 
By Chris Preimesberger  |  Posted 2007-08-07 Email Print this article Print
 
 
 
 
 
 
 

New System p servers feature dual-core, four-thread processors that IBM touts as the world's fastest.

SAN FRANCISCO—IBM on Aug. 6 provided a sneak preview of a key new feature for its new System p data center servers, which are powered by Big Blues next-generation Power6 dual-core, four-thread processors—a chip that a company spokesperson unabashedly called "the fastest in the world." The new features are becoming available this week.
In a briefing at IBMs downtown offices here, several IBM executives offered their own takes on the System p/Power6 story. Included was a demonstration of how an administrator can move an entire partition housing an Oracle database—working in full production and completing between 10,000 and 11,000 transaction per hour—from a four-core, Power6 physical machine to another Power6 machine with 12 cores.
This ostensibly was done in real time and with no effect whatsoever on the running application. IBM engineer Mark Kressin, who ran the demonstration, said that only the power of the Power6 processors could allow IBM to pull something like this off. "What this feature [Live Partition Mobility, a new IBM feature in the Power6 chip] does is take all the memory pages [transactions] that are already completed in the running application and copy them into the new server," Kressin said.
"When the copying catches up to the dirty pages [the ones currently in transaction], the whole application then gets switched over seamlessly to the new server." The Oracle application was running between 10,000 and 11,000 transactions per hour, yet when it was moved from one server to another, no transaction was lost or otherwise affected, Kressin said. Click here to read more about IBMs plans for the Power6 processor. To the roomful of viewers, the demo simply looked like one animated icon being moved from one window (server) to another window (server), with a minimum of instructions being keyed into the control laptop. How an operation like this would take place in the real world was a question yet to be answered. "To do something like this, you must be on the same Fibre Channel network subnet," Kressin said. "We have one customer who did this using server locations about 40 kilometers apart—thats the farthest distance weve seen thus far. You also need Gigabit Ethernet." The whole demonstration process took about 5 to 6 minutes. "This kind of virtualization thing really isnt anything new," analyst Robert Gray of Robert Gray Direct in Newton Center, Mass., told eWEEK. "IBM has been doing this on mainframes for 20 years. The company invested something like $500 million into this research years ago [actually Q4 2000], and it looks like it is starting to bear fruit now." Currently, IBMs System p servers use its Power5+ processor. The Power6 chip launch in May was right in line with the Armonk, N.Y., companys previous public statements that its new chip will be ready for a general release in the second half of 2007. The company has also announced that it will build a supercomputer in Germany that will use a Power6 processor. IBM said that the new chips more than double the frequency offered through Power5+, with a clock speed ranging from 4GHz to 5GHz. The Power6 chips are the first IBM processors built using the companys new 65-nanometer manufacturing process. By using the new manufacturing process, as opposed to the current 90-nanometer process, IBM is trying to double the frequency of its current processors but keep the instruction pipeline at the same depth. This switch means IBM engineers will be able to crank up the speed without adding to the amount of time it will take for an instruction to get through a computation. The processor also has been designed for power efficiency, and it can be configured for high or low voltage, which will allow the platform to scale to the needs of the application that is running. IBM executives have explained that designing flexibility into the microprocessor will allow the chips to run in large and small systems. This plan will allow IBM to have common processor architecture for its server lines, including Systems i, p and z. "The System p 570 can ramp up from four cores, to eight, 12, or 16 core—and it looks just like one big server," said IBM Vice President of Worldwide Linux Strategy Scott Handy. "You just snap them together as you need them. You get really screaming performance and lots of memory—48GB per core." To read about IBMs System i server that will run the Power6 CPU, click here. Big Blue will use the new System p machines to try to persuade current Sun and Hewlett-Packard Unix shops—which are often using numerous open-system, off-the-shelf-type servers—to consolidate hundreds of servers onto fewer, more powerful IBM machines numbering in the dozens. "IBM has completed over 700 Unix migrations since January 2006 [to System p], bringing in about $50 million in revenue," Handy said. "Eighty percent of those are former Sun and HP shops. Over 250 of those were completed this year alone. The virtualization we offer was a big [selling] factor. These were platforms that were going out of business anyway." eWEEK reporter Scott Ferguson contributed to this article. Check out eWEEK.coms for the latest news, views and analysis on servers, switches and networking protocols for the enterprise and small businesses.
 
 
 
 
Chris Preimesberger Chris Preimesberger was named Editor-in-Chief of Features & Analysis at eWEEK in November 2011. Previously he served eWEEK as Senior Writer, covering a range of IT sectors that include data center systems, cloud computing, storage, virtualization, green IT, e-discovery and IT governance. His blog, Storage Station, is considered a go-to information source. Chris won a national Folio Award for magazine writing in November 2011 for a cover story on Salesforce.com and CEO-founder Marc Benioff, and he has served as a judge for the SIIA Codie Awards since 2005. In previous IT journalism, Chris was a founding editor of both IT Manager's Journal and DevX.com and was managing editor of Software Development magazine. His diverse resume also includes: sportswriter for the Los Angeles Daily News, covering NCAA and NBA basketball, television critic for the Palo Alto Times Tribune, and Sports Information Director at Stanford University. He has served as a correspondent for The Associated Press, covering Stanford and NCAA tournament basketball, since 1983. He has covered a number of major events, including the 1984 Democratic National Convention, a Presidential press conference at the White House in 1993, the Emmy Awards (three times), two Rose Bowls, the Fiesta Bowl, several NCAA men's and women's basketball tournaments, a Formula One Grand Prix auto race, a heavyweight boxing championship bout (Ali vs. Spinks, 1978), and the 1985 Super Bowl. A 1975 graduate of Pepperdine University in Malibu, Calif., Chris has won more than a dozen regional and national awards for his work. He and his wife, Rebecca, have four children and reside in Redwood City, Calif.Follow on Twitter: editingwhiz
 
 
 
 
 
 
 

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