Intel, Dell Powering Stampede Supercomputer in Texas

 
 
By Nathan Eddy  |  Posted 2011-09-26 Email Print this article Print
 
 
 
 
 
 
 

Never known for thinking small, the University of Texas teams up with Intel and Dell to produce the Stampede supercomputer.

 

The Texas Advanced Computing Center at the University of Texas at Austin announced that it will deploy and support a world-class supercomputer with comprehensive computing and visualization capabilities for the open science community, as part of the National Science Foundation's "eXtreme Digital" (XD) program. The new system, called Stampede, will be built by TACC in partnership with Dell and Intel, and is expected to be up and running in January 2013.

When completed, Stampede will comprise several thousand Dell Zeus servers, with each server having dual eight-core processors from the forthcoming Intel Xeon Processor E5 family (formerly code-named Sandy Bridge) and each server with 32 gigabytes of memory. This production system will offer almost 2 petaflops of peak performance, double the current top system in XD.

The cluster will also include Intel Many Integrated Core (MIC) co-processors code-named "Knights Corner," providing an additional 8 petaflops of performance. Intel MIC co-processors are designed to process highly parallel workloads and provide the benefits of using the most popular x86 instruction. In addition, Stampede will offer 128 next-generation Nvidia graphics processing units (GPUs) for remote visualization, 16 Dell servers with 1 terabyte of shared memory and 2 GPUs each for large data analysis, and a high-performance Lustre file system for data-intensive computing.

"Stampede will be one of the most powerful systems in the world and will be uniquely comprehensive in its technological capabilities," said TACC Director Jay Boisseau. "Many researchers will leverage Stampede not only for massive computational calculations, but for all of their scientific computing, including visualization, data analysis and data-intensive computing. We expect the Stampede system to be a model for supporting petascale simulation-based science and data-driven science."

Altogether, Stampede will have a peak performance of 10 petaflops, 272 terabytes (272,000 gigabytes) of total memory and 14 petabytes (14 million gigabytes) of disk storage. As part of the Stampede project, future generations of Intel MIC processors will be added when they become available, increasing Stampede's aggregate peak performance to at least 15 petaflops. Stampede also has potential for additional upgrades.

"Stampede is the most powerful x86-based Linux HPC cluster announced for deployment in the U.S. at this time," Boisseau said. "The system builds on TACC's history of continuously deploying larger and more powerful x86 Linux clusters that enable new scientific breakthroughs. It will also be the first large-scale implementation of Intel's MIC architecture-based products."

However, to sustain tens of petaflops of performance and achieve exascale computing, Boisseau said, industry and the science community will have to move to highly data parallel processors. "You get so much potential performance out of one of these highly data parallel processors like a GPU or an Intel MIC architecture-based product," he explained. "We think this architecture is the quickest path for many applications to sustain petascale performance and to eventually build exascale systems."

The estimated investment will be more than $50 million over four years, and the Stampede project may be renewed in 2017, which would enable four additional years of open science research on a successor system. Stampede will be operated and supported for the first four years by TACC, Dell and a team of cyber-infrastructure experts at the University of Texas at Austin, Clemson University, University of Colorado at Boulder, Cornell University, Indiana University, Ohio State University and the University of Texas at El Paso.

 
 
 
 
 
Nathan Eddy is Associate Editor, Midmarket, at eWEEK.com. Before joining eWEEK.com, Nate was a writer with ChannelWeb and he served as an editor at FierceMarkets. He is a graduate of the Medill School of Journalism at Northwestern University.
 
 
 
 
 
 
 

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