At an IEEE conference in December, Intel and IBM will each publish several technical papers that will plot their 32-nanometer microprocessor road maps for the next year. Taiwan Semiconductor Manufacturing will also present a paper that will detail its efforts at 32-nanometer chip manufacturing. In addition to these 32-nm processor papers, IBM scientists will describe what is being called the world's smallest functioning 22-nm SRAM cell.
Intel,
IBM
and Taiwan Semiconductor Manufacturing are planning to publish a series of new
technical papers at a December conference that will detail each of their
efforts to manufacture 32-nanometer microprocessors.
All three of these companies are scheduled to present their papers and
analysis at the IEEE's International Electron Devices conference in San
Francisco, which starts Dec. 15. A number of abstracts
for these and other technical papers are now available at the
IEEE Web site.
In addition to these papers,
IBM
and its alliance of chip development partners, which include Advanced Micro
Devices, Freescale Semiconductor, STMicroelectronics, Toshiba, and the College
of Nanoscale Science and
Engineering of the University of Albany
in New York, will present on
paper that will describe their efforts to produce a 22-nm SRAM (static RAM)
memory cell.
In the paper, IBM and its partners are
calling the SRAM the smallest functioning SRAM
cell ever made.
The push toward 32- and then 22-nm processors is considered an essential
mission of the semiconductor industry as devices from cell phones to notebooks
continue to shrink and customers and IT buyers demand better performance and
more battery life from these mobile devices. On the high end, these chips will
also allow companies to build new types of servers and high-performance
computers that use less power while increasing the performance.
For its part,
Intel
has already announced that it will offer 32-nm microprocessors-code-named "Westmere"-in
2009. The paper at the IEEE conference, however, is one of the first times
Intel engineers will detail their efforts to produce these chips.
When these processors do come to market, they will be based on Intel's
Nehalem microarchitecture. In November,
Intel
will begin offering the first chips based on Nehalem for high-end PCs and
gaming systems. These first chips are built on the company's current 45-nm
manufacturing process.
The 32-nm Intel chip will use the company's second-generation high-k metal
gate technology, which reduces power leakage-the electricity wasted while the
transistors are idle-and helps improve performance. Intel's paper will also
detail the company's efforts to produce these chips using "193-nm immersion
lithography" and how it developed low-k interconnect dielectrics or insulators
within the chips.
The SRAM test chips that Intel engineers
will detail will contain 2 billion transistors, a significant improvement
compared with 45-nm chips, which contained at 800 million transistors when
those processors came to market in November 2007.
At the same time that Intel is presenting its paper, IBM
and TSMC will each present their methods for producing 32-nm chips. In the IBM
paper, engineers will discuss how they developed low-power CMOS
technology with a high-k metal gate to stop power leakage. CMOS
(complementary metal oxide semiconductor) is an integrated circuit that is an
important step in developing a fully functioning microprocessor.
In their paper, IBM engineers said these
chips will eventually be used in high-data-rate applications such as notebooks.
Finally,
TSMC,
an independent foundry that manufacturers chips for other IT vendors, will
offer a paper that looks at its 32-nm foundry technology. In the paper, TSMC
engineers said they will use a high-k metal gate that uses the element hafnium
as a dielectric. Intel also uses hafnium in its high-k metal gate manufacturing
process.
TSMC will detail some of these technological features in a test SRAM
chip.
Email
Print
