Intel Offers Nehalem Details

Intel is turning the spotlight on Nehalem.

After spending most of 2008 detailing its chips and platforms for new lines of mobile Internet devices and low-cost notebooks, Intel is now offering some additional details about Nehalem—the company’s line of microprocessors based on a new microarchitecture that is set to debut later this year.

In a conference call that set the stage for this year’s Intel Developer Forum in China, Pat Gelsinger, senior vice president of the Digital Enterprise Group, said the first of the Nehalem chips will offer four processing cores and appear first in servers and high-end desktops later this year before entering the broader market in 2009.

The first Nehalem processors will go into production by the fourth quarter of 2008.

The Santa Clara, Calif., chip maker began talking about Nehalem in earnest at the 2007 IDF in San Francisco. These processors, which will initially be based on a 45-nanometer manufacturing process, will scale from two to eight processing cores and offer four times the bandwidth of Intel’s current crop of Xeon processors.

“We are describing Nehalem as both dynamically scalable and modular in its design,” Gelsinger said.

“What do we mean by dynamically scalable?” Gelsinger added. “It means that that we have built technologies into it that from a frequency, performance, power and design perspective [allow Nehalem] to scale from high-performance characteristics to low-power characteristics. It will respond to single-threaded workloads and multithreaded workloads. It will be able to address greater performance as well as great energy efficiency.”

The first of the Nehalem chips will offer 8MB of Level 3 cache that is shared across all the cores—each core has 256KB of L2 cache—as well as an integrated memory controller and a new technology dubbed QuickPath interconnect.

The QuickPath technology allows Intel to integrate the memory controller within processor, and it also connects the Nehalem processor to another component on the motherboard or another microprocessor. Within a two-socket server, the QuickPath will offer two links per CPU, which Intel said will produce 25.6G bps of bandwidth per link.

The integrated memory controller will also support DDR3 (double data rate 3) memory instead of fully buffered DIMMs (dual in-line memory modules). DDR3 uses less power than full-buffered DIMMs, which will help boost the overall performance per watt of Nehalem.

Finally, these new processors will support two instructional threads per core, which Gelsinger said will allow the chips to support large workloads, such as database applications, that are optimized for multithreaded environments.

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