IT & Network Infrastructure : Intel's 3D Tri-Gate Transistor Breakthrough: A Look Inside

 
 
By Chris Preimesberger  |  Posted 2011-05-05 Email Print this article Print
 
 
 
 
 
 
 
 
Intel is taking nano-scale chip design literally to another level. After more than five decades of putting flat (or planar) transistors to work in billions of chips in billions of digital devices ranging from big-iron mainframes to minuscule embedded sensors, Intel said May 4 that it now will build the tiny processing units in three dimensions, instead of two. They are called Tri-Gates, and Intel first disclosed the technology that goes into this chip design in 2002. Intel's 3D Tri-Gate transistors enable chips to operate at lower voltage with lower leakage, providing a combination of improved performance and energy efficiency never before seen in the chip industry, Intel Senior Fellow Mark Bohr said. The channels of electricity on three sides of the vertical fin structure make up the 3D nature of the transistor. The 22-nanometer 3D Tri-Gate transistors (a nanometer is one-billionth of a meter) provide up to 37 percent performance increase at low voltage compared with Intel's currently shipping 32nm planar transistors. This significant gain signifies that they are ideal for use in small handheld devices. These new transistors will reside on Intel's soon-to-come 22nm Ivy Bridge processors, due out late this year. Here are some details on how these Tri-Gates work.
 
 
 

Tri-Gate 3D Transistors: Low Power or High Performance

Intel Senior Fellow Mark Bohr, who's been working on the 3D transistors for a full decade, said the capabilities give chip designers the flexibility to choose transistors targeted for low power or high performance, depending on the application. "Of course, the Tri-Gates are very capable at both," Rohr said.
Tri-Gate 3D Transistors: Low Power or High Performance
 
 
 
 
 
Chris Preimesberger Chris Preimesberger was named Editor-in-Chief of Features & Analysis at eWEEK in November 2011. Previously he served eWEEK as Senior Writer, covering a range of IT sectors that include data center systems, cloud computing, storage, virtualization, green IT, e-discovery and IT governance. His blog, Storage Station, is considered a go-to information source. Chris won a national Folio Award for magazine writing in November 2011 for a cover story on Salesforce.com and CEO-founder Marc Benioff, and he has served as a judge for the SIIA Codie Awards since 2005. In previous IT journalism, Chris was a founding editor of both IT Manager's Journal and DevX.com and was managing editor of Software Development magazine. His diverse resume also includes: sportswriter for the Los Angeles Daily News, covering NCAA and NBA basketball, television critic for the Palo Alto Times Tribune, and Sports Information Director at Stanford University. He has served as a correspondent for The Associated Press, covering Stanford and NCAA tournament basketball, since 1983. He has covered a number of major events, including the 1984 Democratic National Convention, a Presidential press conference at the White House in 1993, the Emmy Awards (three times), two Rose Bowls, the Fiesta Bowl, several NCAA men's and women's basketball tournaments, a Formula One Grand Prix auto race, a heavyweight boxing championship bout (Ali vs. Spinks, 1978), and the 1985 Super Bowl. A 1975 graduate of Pepperdine University in Malibu, Calif., Chris has won more than a dozen regional and national awards for his work. He and his wife, Rebecca, have four children and reside in Redwood City, Calif.Follow on Twitter: editingwhiz
 
 
 
 
 
 

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