Intel's New 3D Transistors: More Powerful, Less Power-Hungry

 
 
By Chris Preimesberger  |  Posted 2011-05-04 Email Print this article Print
 
 
 
 
 
 
 

Intel said it now will build its microscopic processing units in three dimensions, instead of two. They are called Tri-Gates, the technology of which was first disclosed by Intel in 2002.

SAN FRANCISCO-Intel, after a decade of research and development, is adding a literal new dimension to those microscopic transistors that fill up IT processors.

Remember transistors? Those are the millions, and often billions, of microscopic elements embedded inside chips that make all of the digital devices we use actually work-something that most people don't know or take for granted.

After some five decades of putting flat (or planar) transistors to work in billions of digital devices ranging from big-iron mainframes to minuscule embedded sensors, Intel said May 4 that it now will build the tiny processing units in three dimensions, instead of two (see image at bottom of this article). They are called Tri-Gates, the technology of which was first disclosed by Intel in 2002.

Intel's 3D Tri-Gate transistors enable chips to operate at lower voltage with lower leakage, providing a combination of improved performance and energy efficiency never before seen in the chip industry, Intel Senior Fellow Mark Bohr told reporters at a May 4 press conference here.

Low Voltage, High Performance

Bohr, who's been working on this project for a decade, said that the capabilities give chip designers the flexibility to choose transistors targeted for low power or high performance, depending on the application. "Of course, the Tri-Gates are very capable at both," Rohr said.

The 22nm 3D Tri-Gate transistors, which will live first on Intel's new Ivy Bridge chips, provide up to 37 percent performance increase at low voltage compared with Intel's currently shipping 32nm planar transistors. This significant gain indicates that they are ideal for use in small handheld devices, which operate using less energy to "switch on and off, off and on," Bohr said.

Alternatively, the new transistors consume less than half the power when at the same performance as 2D planar transistors on 32nm chips, Bohr said.

View a video demonstration of the Tri-Gate on YouTube.

This breakthrough process changes forever the IT processor-making business. Once Intel's fabrication plants get rolling at full speed later this year to produce these new 22-nanometer chips, the flat designs will be phased out completely.

"There are no planar plans on our 22-nanometer [a nanometer is one-billionth of a meter] technology. It's all Tri-Gate. We can wave goodbye to planar transistors," Bohr said.

Transistors, of course, are the basis for Moore's Law. Moore's Law, published in a magazine article in 1965 by Intel co-founder Gordon E. Moore, describes a long-term trend in the history of computing hardware that "the number of transistors that can be placed inexpensively on an integrated circuit doubles approximately every two years." This theorem has been accurate for more than half a century and is expected to continue until 2015 or 2020 or later.

Moore Himself Adds Perspective

Moore, 82, could not be at the press event on May 4 but sent along a statement relevant to the news announcement.

"For years we have seen limits to how small transistors can get," Moore said. "This change in the basic structure is a truly revolutionary approach, and one that should allow Moore's Law, and the historic pace of innovation, to continue."

At the press conference, Intel demonstrated a 22nm Ivy Bridge microprocessor that will be the first high-volume chip to use the Tri-Gates. Bohr and Intel Executive Vice President and General Manager of the Architecture Group Dadi Perlmutter showed reporters and analysts how it worked in a netbook and in a small server.


It doesn't look like a huge change from here, but the Intel Tri-Gate transistor (right), by going perpendicular with its power flow through the gateway (yellow area), as opposed to the standard planar version (left), is about to change the processor industry. (Image courtesy of Intel.)

 
 
 
 
Chris Preimesberger Chris Preimesberger was named Editor-in-Chief of Features & Analysis at eWEEK in November 2011. Previously he served eWEEK as Senior Writer, covering a range of IT sectors that include data center systems, cloud computing, storage, virtualization, green IT, e-discovery and IT governance. His blog, Storage Station, is considered a go-to information source. Chris won a national Folio Award for magazine writing in November 2011 for a cover story on Salesforce.com and CEO-founder Marc Benioff, and he has served as a judge for the SIIA Codie Awards since 2005. In previous IT journalism, Chris was a founding editor of both IT Manager's Journal and DevX.com and was managing editor of Software Development magazine. His diverse resume also includes: sportswriter for the Los Angeles Daily News, covering NCAA and NBA basketball, television critic for the Palo Alto Times Tribune, and Sports Information Director at Stanford University. He has served as a correspondent for The Associated Press, covering Stanford and NCAA tournament basketball, since 1983. He has covered a number of major events, including the 1984 Democratic National Convention, a Presidential press conference at the White House in 1993, the Emmy Awards (three times), two Rose Bowls, the Fiesta Bowl, several NCAA men's and women's basketball tournaments, a Formula One Grand Prix auto race, a heavyweight boxing championship bout (Ali vs. Spinks, 1978), and the 1985 Super Bowl. A 1975 graduate of Pepperdine University in Malibu, Calif., Chris has won more than a dozen regional and national awards for his work. He and his wife, Rebecca, have four children and reside in Redwood City, Calif.Follow on Twitter: editingwhiz
 
 
 
 
 
 
 

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