Itanium to Take Spotlight at ISSCC

 
 
By Jeffrey Burt  |  Posted 2003-02-10 Email Print this article Print
 
 
 
 
 
 
 

Itanium's cache size is one of the topics slated for discussion at this week's ISSCC show in San Francisco.

Larger cache sizes will continue to be a driver as the 64-bit Itanium chip continues to evolve, according to Intel Corp. officials. The next generation of the Itanium 2 chip will come in three versions with either 3MB, 4MB or 6MB of Level 3 cache, and the two cores in the Itanium chip set for release in 2005 will each have their own Level 3 cache. Those are some of the details of the next round of Itanium 2 chips that that Intel officials will talk about this week at the International Solid-State Circuits Conference in San Francisco. Last month, Intel altered its Itanium roadmap, with plans to add another Itanium 2 chip next year and put dual-core processing into its Montecito processor. The dual-core technology—which enables Intel to put two full processors onto the same piece of silicon and fit it into the same package, essentially doubling the processing power—initially was expected to appear in chips after Montecito, which is scheduled for release in 2005.
Larger on-die caches enable the processor to access data more quickly and reduce the amount of time it takes to seek memory data off of the chip.
The next Itanium 2 chip, code-named Madison, will not only have three different L3 cache sizes, but also will run at three different frequencies, including 1.5GHz, according to Nimish Modi, general manager of Intels Enterprise Processor Division. "The combination of different cache SKUs and different frequency SKUs will allow us to offer in the market three different price points in Madison," Modi said, declining to say what the other two frequencies will be. For Montecito, each of the cores will have their own L3 cache, which will give it more than two times the cache of preceding processors, Modi said. The chip also will have an arbiter that will work as the interface between the two cores and the system bus, processing requests from the core for the systems bus. That will enable Intel to offer the dual-core technology within the same footprint as the Madison and Madison 9M, which is due out next year, Modi said.
OEMs and enterprises will then be able to protect their current investments by simply trading out chips when they want more processing power rather than by having to bring in entire new systems. The ISSCC show comes a week before Intel hosts its spring Intel Developers Forum, in San Jose, Calif. At that show, the Santa Clara, Calif., chip maker is expected to discuss Deerfield, its lower-power chip designed for high-density rack and blade architectures, and its Centrino family of mobile products, which will include the Banias chip and related chipsets and will be launched in March. Deerfield will be released in the second half of the year. Industry observers also expect to learn more about Prescott, the chip many say will become Pentium 5 and will be built using the .09-micron process, which will shrink the die size and cut Intels production costs.
 
 
 
 
 
 
 
 
 
 
 

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