Intel Corp. has redrawn its server processor road map for the next few years.
The Santa Clara, Calif., chip giant on Monday said it will push back the introduction of some of its Itanium chips, including moving the launch of its dual-core Itanium chip, dubbed Montecito, back by several months. Montecito had been scheduled to debut early next year, but instead will come out at mid-2006, Intel said. The chip maker countered the bad with good, saying it will add a new multicore Xeon MP processor, code-named Tigerton, in 2007.
Although not exactly a win in public relations, the Itanium delay, which an Intel spokesman said related to the quality of the chips, isnt likely to have a major immediate impact on the high-end server market. That world, in which Intel aims to compete with IBMs Power processors and Sun Microsystems Inc.s UltraSPARC for high-end servers, moves slowly, when compared with x86 servers based on Xeon or Advanced Micro Devices Inc.s Opteron. But even the Xeon MP change, which Intel said was designed to increase performance, is far enough out that its impact is hard to determine, analysts said.
"I dont see either as earth-shattering," said Gordon Haff, analyst with Illuminata Inc. "You dont want to see things slip. But, at the end of the day, if Montecito gets delivered per this revised schedule and the performance increase is in the range of what Intel has talked about [the company has described Montecito as offering a two times increase], it will still give HP and SGI [the chips main customers] a competitive high-end processor offering."
Indeed, Hewlett-Packard Co., in a statement supporting the chip, said it will offer Montecito-based HP Integrity servers when Intel has them available.
When it comes to the Xeon MP changes, "we dont have an awful lot of information here, but I think we can assume for purposes of discussion that Intel will release a decent performance architecture on Tigerton," Haff said. "How it will perform relative to [rival AMDs] Opteron in that time frame, who knows. Its two years away."
Intels Tigerton Xeon MP chip will take the place of Whitefield, a previously disclosed processor that was expected to include four processor cores. Tigerton will also incorporate multiple processor cores—its likely to be four, given what was known about Whitefield—along with a new and as yet unnamed front side bus or pipeline for carrying data to and from the processor. The chip will come inside a new platform dubbed Caneland and generally designed for servers with four or more chips in them. Caneland will supersede a platform called Reidland, which would have accommodated Whitefield.
"We anticipated having performance leadership in Whitefield at that time [or 2007]. We had an opportunity to improve that performance advantage, i.e., deliver even more performance, and we took it," said Scott McLaughlin, an Intel spokesman. The change, he said, was part of Intels standard process of planning.
The new bus will use a point-to-point connection for each processor, versus Intels current shared bus approach, where more than one chip shares a bus, McLaughlin indicated.
The new bus will not incorporate a memory controller, nor will it be the next-generation interconnect that the company has also discussed offering, he said.
Thus, Intel appears to be pursuing a hybrid approach as an interim step between todays shared bus and the next-generation interconnect, Haff said.
The "possibilities are that [Intel] feels at that timeframe they can get better performance. Or it may be a time-to-market issue. It might decrease the risk of schedule slippage by going to an architecture thats more traditional," he said.
Intels McLaughlin declined to offer more details on the bus.