A new generation of networking chip startups is attempting to find a path into business networks by making 10G-bps networking gear more palatable to their IT budgets.
The companies, which include ClariPhy Communications and KeyEye Communications, are crafting optical physical layer interface chips and copper media transceivers, respectively, that they say network equipment makers can use to boost the bandwidth of their 10G-bit gear while also lowering prices.
Although they come at the market from different angles, the two companies aim to convince network gear makers that using their chips could cut the cost of equipment upgrades by hundreds per port, creating an opportunity to speed up the adoption of 10G-bit connections—still fairly rare—in network backbones and data centers. Drop the cost of 10G-bit gear enough, they argue, and it will sway businesses to upgrade.
ClariPhy, a 25-employee startup that emerged in February, plans to offer a chip that can save companies money by bumping the bandwidth of existing network cables. Its digital signal processor-based PHY (physical layer) for 10 Gigabit Ethernet, most likely to be built into line cards used by network switches, will make it possible for companies to continue using their existing 2.5G-bit multimode optical network cables, but it promises to bump the bandwidth of those cables to 10G bps.
The chip, which will conform to the forthcoming IEEE 10GBase-LRM standard for 10 Gigabit Ethernet over optical cables, is able to offer the increase because its built-in digital-signal processor can compensate for distortions created by sending the high-speed signals, said Paul Voois, ClariPhys CEO, in Irvine, Calif.
"Whats going to save them cost going to 10 Gigabit is not having to replace their cable," Voois said.
Following the 10GBase-LRM standard means companies can cut costs by employing fewer lasers for sending networking signals via optical cables than current chips based on than todays 10GBase-LX4 standard. But ClariPhys secret sauce is in the way it employs its electronic dispersion compensation techniques, making use of the DSP to compensate for signal distortion, in addition to using CMOS, a standard method for manufacturing processors, memory and other chips, Voois said.
ClariPhys first PHY chip is still in development, allowing it to dovetail with the 10GBase-LRM standard, expected to be finalized later this year. The company expects to sample the chip to customers later this year. Thus it wont be available in equipment until 2007, Voois said.
ClariPhy ultimately aims to use its chips to help drive the per-port cost of 10 Gigabit Ethernet to less than $100 for equipment makers. Right now that cost is about $500, Voois said. Lowering manufacturers costs would allow them to, in turn, offer lower prices to business customers.
"For 10 Gigabit to really happen, you need to get to 10 times the performance at three times the cost," Voois said. Historically, "when IT managers are faced with that equation, theyll pay" to upgrade, he said.
It will take time for prices to come down, however, and there are still strides to be made in port density. But, as the company sees it, theres plenty of opportunity in network backbones where there are about 100 million existing ports that use multimode fiber, which could be upgraded to 10G-bit speeds. Its chips will also work to enable data center computer interconnects, Voois said.