Intel is planning to offer some of the first details about how its engineers will switch the company's processor manufacturing from the current 45-nanometer model to a newer, smaller 32-nm design in 2009.
At the International Electron Devices meeting in San Francisco, which starts Dec. 15, Intel engineers will present seven technical papers, including one that details Intel's efforts to create the company's first 32-nm microprocessors. (A nanometer is one billionth of a meter.)
Intel is scheduled to switch to 32-nm processors in late 2009. These processors-code-named "Westmere"-will still be based on the Nehalem microarchitecture that Intel released at its Developer Forum in August. The first of the Nehalem processors, called Core i7, are built on the company's 45-nm manufacturing process.
While Intel is offering details about its efforts to bring new generations of processors into the mainstream market, it's not the only company planning some new disclosures at the conference. IBM, along with its partners that include Advanced Micro Devices, Freescale Semiconductor, STMicroelectronics, Toshiba, and the College of Nanoscale Science and Engineering of the University of Albany in New York, will present on a paper that will describe their efforts to produce a 22-nm SRAM (static RAM) memory cell.
In addition to Intel and IBM, engineers from Taiwan Semiconductor Manufacturing are scheduled to present their own road map for manufacturing 32-nm processors.
The drive toward 32 nm, and then the switch to 22 nm, is considered one of the next critical steps in processor development.
As the size of desktops, notebooks and other devices continues to shrink, and as both business buyers and consumers demand longer battery life and better performance from these devices, companies such as Intel and AMD have to find new ways of creating processors that use less power but still offer a significant bump in the overall performance.
The smaller sizes also mean that chip companies can add new features to their processors, such as larger cache sizes.