While Intel Corp. and IBM have garnered a lot of attention with upcoming enhancements to their respective Itanium and Power processors, users of high-end SPARC systems similarly can expect multicore and multithreaded processing capabilities in coming revisions of SPARC chips.
At the Microprocessor Forum this week in San Jose, Calif., Sun Microsystems Inc. and Fujitsu Computer Systems Corp. will unveil road maps for their SPARC chips that include dual-core processing that will be able to run multiple threads simultaneously and will crank up performance and memory capacity.
Chip makers are pursuing dual-core processing to get more power onto a single die and multithreading to improve instruction processing within the chip.
In the first half of next year, Sun will introduce the UltraSPARC IV, which will be used in the Santa Clara, Calif., companys midrange and high-end servers, ranging from the four-way Sun Fire V480 to the 106-processor Sun Fire 15K. It will also feature Suns Chip Multithreading technology. Suns Gemini low-end server chips will also get two cores.
Within three or four years, Sun will shift to a 65-nanometer production process for the third generation of the UltraSPARC IV, which officials said will give the chip a 30-fold improvement over the UltraSPARC III.
Telus Business Solutions, a unit of Telus Communications Inc., uses Suns blade servers, the platform that will host the first chip multithreading technology built on the 65-nm process in 2006. Craig Richardson, assistant vice president of hosting and managed applications at Telus, said multicore processing will reduce the complexity and increase the performance of Suns offerings.
"Any time a vendor can increase the processing power of a server while maintaining or decreasing the [physical space], its a good news story for us," said Richardson, in Vancouver, British Columbia.
For its part, Fujitsu will continue ramping up its Solaris-compatible SPARC64 V chip, increasing its clock speed to 1.6GHz toward the end of the year. It will increase the speed further next year and increase the L2 cache from 2MB to 4MB, officials said.
In late 2005 or early 2006, the Sunnyvale, Calif., company will roll out Version VI of the chip, which will be built using a 90-nm process. The chip will feature two cores with shared cache, which lets the CPU determine how much cache to give to each core, increasing utilization and flexibility. The SPARC64 VI will also have larger cache sizes on the cores, officials said. In addition, Fujitsu is readying a bus technology that will allow for higher throughput. Although the first Version VI iterations will be dual-core, the product will move to four cores by the sixth and seventh revisions.