Its not an easy time to be Intel Corp. or Advanced Micro Devices Inc. The launch of AMDs Opteron emphasizes the difference between their technology strategies, but the companies are just placing different bets in the same casino. Both companies hope that the mass-market economics of high-volume processor production will draw resource-limited server manufacturers—and cost-conscious enterprise buyers—into their 64-bit game at the expense of established platforms.
Server processing power is clearly a buyers market. Intel has been almost embarrassed by its success in continuing to squeeze higher clock rates, though not proportional performance gains, from the aging Pentium architecture and its Xeon server-optimized configurations.
The question, though, is how much opportunity remains for hardware to analyze an ever-more-rapid flow of Pentium-style instructions, on the fly, in search of opportunities to transform them into entwined (but not entangled) streams of concurrent operations. Two different answers to that question define the difference between the Itanium and Opteron as the next logical step for server CPUs.
Intel is betting that on-chip instruction scheduling hardware, which emerged on x86 chips in the late 1990s to inject new life into 1980s-style code, is nearing its limit. With the Itanium, Intel proposes to examine programs when they are compiled into their executable form and encode concurrent operations ahead of time. Intel calls this approach EPIC, for Explicitly Parallel Instruction Computing, and it is the genuine difference between the Itanium and AMDs x86-64.
EPICs drawback is that the core of the Itanium no longer offers an effective upward-compatible path to existing x86 code; its speed in running that 32-bit code has proved to be disappointing. Intel and its Itanium design partner, Hewlett-Packard Co., have therefore repositioned this facility as a convenience for running code that is either noncritical to performance or unavailable for porting to Itanium native form.
The Itaniums 32-bit x86 hiccup creates a major opportunity for AMD, which is betting that its cheaper to perform a miracle in hardware—and duplicate it in volume-produced microprocessors—than to undertake the worldwide drudgery of revamping the software base.
The Opteron and its desktop-oriented sibling, the Athlon 64 (promised in September), throw all AMDs talent at the challenge of running x86 instructions as quickly as possible—while at the same time introducing 64-bit hardware and instruction set extensions.
If industry infrastructure vendors and software developers expect AMD to do well, IT buyers will soon see a host of optimized driver software, middleware and applications for x86-64 that could easily add tens of percentage points to the overall performance of Opteron and Athlon 64 machines.
Whats often overlooked is that AMDs and Intels strategies are more similar than different. On the fundamentals, its safe to bet that computing requirements in every economic segment will expand the market for 64-bit processors like the Opteron and Itanium. Both offer the ability to work with growing collections of data. Both have the intrinsic computing speed, and the multiway scalability, to perform the next generation of critical enterprise tasks.
But 64-bit computing is not a 21st- century innovation; enterprise hardware builders such as IBM, Sun Microsystems Inc. and HP already offer respected families of 64-bit systems that are earning their keep in many applications, though failing to achieve the low mass-market prices required for broader adoption. The question that tests the nerve of IT hardware makers is this: How many high-end processor architectures can the industry afford to continue to develop and build?
Each new generation of fabrication plants raises the stakes. Despite the unquestioned technical merits of designs like the late, lamented Alpha, only a handful of processor families can survive.
AMD and Intel need to see the hole card of the enterprise IT buyer. Will that card show readiness to acquire and assimilate a whole new base of operating systems, enterprise middleware and applications to take advantage of the Itanium architectures completely new instruction set? Or will it reveal the combination of technical caution and commercial risk acceptance that could bring buyers to AMDs door, seeking a 64-bit superset of the well- established x86?
Technology Editor Peter Coffee can be contacted at firstname.lastname@example.org.