AMD Puts Focus on Power Efficiency of Carrizo
Power efficiency is a growing concern for many businesses, Mohin said, noting that 60 percent of Fortune 100 companies have established goals for reducing greenhouse gas emissions. Businesses "are starting to be forward-looking and starting to ask the right questions," said Aditi Mohapatra, associate director of the ICT practice at Business for Social Responsibility. For AMD, reaching the goals set forth in its 25x20 initiative is daunting, according to Sam Naffziger, AMD corporate fellow. Moore's Law called for the doubling in the number of transistors on chips every 18 to 24 months, leading to improvements in both performance and power efficiency. However, gains in energy efficiency have slowed since about 2000 due to the challenges inherent in shrinking the components inside the chips. AMD's goal is to exceed the historical efficiency trend predicted by Moore's Law by at least 70 percent, Naffziger said during a presentation. Carrizo gets AMD on its way. According to Naffziger, for the vendor to reach its goal by 2020, each chip generation will have to improve its power efficiency 1.7 times over the previous generation. AMD got a 2.4-times improvement with Carrizo. For its engineers, the challenge was improving the performance and power efficiency while staying within the same 28nm node as Kaveri. Naffziger outlined some of the steps the engineers took when developing Carrizo. Among them were a high-density library design, better power management between the CPU and GPU on the die, and a reduction in the power needed for communications between the CPU and GPU. They increased the Level 1 cache while reducing the L2 cache, and reduced power consumption through better clock gating and other array changes.However, the engineers also had to balance the drive for power reduction with the need for performance gains, Naffziger said. "This isn't just about low power and efficiency, because low power isn't anything without performance," he said. The company was able to increase the frequency of the Excavator core—which is optimized for a 15-watt design point—by 39 percent. In addition, various enhancements—from the larger L1 cache and pre-fetch improvements to better branch prediction and new instruction support—translate to a 10 percent to 15 percent improvement in instructions per clock. On the graphics side, AMD was able to increase the frequency up to 18 percent, and Carrizo is able to use all eight graphics cores, while Kaveri could use just six.
The chip's shared memory interface also saves power, he said.