Intel Digs Deeper Into 14nm Broadwell-Y SoC for Ultrathin Laptops
Eventually the 14nm Broadwell design will run throughout a range of systems, from PCs to servers, as more of the chip family is rolled out into 2015. "It's going to cover, eventually, top to bottom," according to Natarajan. The new SoC will feature the second generation of Intel's Tri-Gate transistor architecture, a three-dimensional design first introduced in 2011 that is aimed at improving the chip's performance while keeping a lid on power consumption. It's Intel's version of the FinFET 3D transistor design that other chip makers, including Taiwan Semiconductor Manufacturing Corp. (TSMC), Globalfoundries and Samsung, are working on. Natarajan said that while those other companies are still working to get their first-generation technology completed, Intel is about to launch its second-generation Tri-Gate architecture. In the latest Tri-Gate technology, Intel reduced the distance between the elements, while also making the "fins" on the architecture thinner and taller than those in the 22nm Haswell chips, reducing the number of fins needed. This helped improve the density and lower the power of Broadwell. The combination of the 14nm design and new Tri-Gate technology means greater SRAM (static random access memory), and the new transistors offer greater performance and less power leakage than previous generations, Natarajan said. The 14nm architecture also is helping reduce the cost-per-transistor, which he said is "a key trend for Moore's Law."In addition, the second generation of Intel's Fully Integrated Voltage Regulator (FIVR) and the movement of the 3DL Modules from the SoC's package substrate to underneath the die improved power delivery in the chip, while Intel also brought enhanced power management features—including enhanced Turbo Boost—improved energy efficiency and performance, according to Jourdan. In the Converged Core, some of the improvements over Haswell include a larger out-of-order scheduler, a faster floating-point multiplier, faster virtualization round trips and performance features that were designed with a performance to power ratio of 2:1, all of which add up to greater performance and improved energy efficiency.
Getting Broadwell to meet the challenge of fanless designs—with thickness of 8mm to 10mm and a 10.1-inch display—required developing an SoC that consume 3 to 5 watts of power. Through optimizations in the 14nm design—in such areas as capacitance, minimum operating voltage and low-voltage transistor performance—Intel was able to deliver twice the power reduction than simply reducing the scale of the chip would bring.