SAN JOSE, Calif.—Intel Corp.s enterprise processor road map will evolve into an ever more complex matrix, where customers will be asked to make choices based on multiprocessing and thermal power.
The result will be an enterprise environment where IT managers and enterprise OEMs will design for multiple processor threads running on chips with multiple processor cores, in systems housing multiple processors.
"We can move to a place of multiple threads on a single core and multiple cores on a single package, then multiple processors in a single system," said Ajay Malhotra, general manager of Intels enterprise marketing and planning group, in an interview at the Intel Developer Forum here. "Reducing computational time from a week to a day … is super exciting."
On Tuesday, Intel President Paul Otellini added two new names to Intels enterprise road map: "Tulsa," a 32-bit Xeon that will contain two processing cores, and "Tanglewood," a multicore Itanium chip. Intel did not disclose when either chip will ship, but the companys new public processor road map does not show either chip shipping before 2005.
Analysts said they suspect that Intel will have to combine two cores on a single die or else lose any speed advantage multicore implementations would offer. When a chip searches for data off-chip in main memory, tens or even more than 100 processor cycles could be wasted waiting for data. Looking for the same data in an on-chip cache can take a fraction of the time, keeping the processor "fed" with data at its most efficient.
"I would have to believe theyre talking about multiple cores on die," said Peter Glaskowsky, editor of The Microprocessor Report and an analyst with In-Stat/MDR. "It just makes sense."
Still, Malhotra said, thats not necessarily the case. "It doesnt have to be individual cores on a die—it could be a multichip package," he said of the Tulsa and Tanglewood. The decision, Malhotra admitted, hasnt been made.