Call it chip week in San Francisco. Multicore processors and the work that goes into building them will be the talk of the town the week of Sept. 25 as Intel kicks off its fall Developer Forum.
The chip maker, which holds developer forums twice annually, will again occupy San Franciscos Moscone West convention center to deliver details about its forthcoming plans to its partners, press and analysts. Intel CEO Paul Otellini will kick off the event with a keynote address.
But where much of Intels spring 2006 Developer Forum was focused turning the ship—Intel used the March 2006 event to announce a new focus on energy efficient performance, launch its Core Microarchitecture and preview its now shipping Core 2 Duo and Xeon 5100 processors—the fall forum, which starts on Sept. 26, will focus on the course that now lies ahead for the chip maker.
Since this spring, it has shed a number of businesses as well as several thousand employees in an effort to become more efficient and more nimble, while at the same time launching 40 new processors and supporting chip sets.
Otellini, in his speech, is thus expected to set the direction for the coming months and years for the company.
The chief executive will discuss Intels focus on performance and energy efficiency—the two are not mutually exclusive, the chief executive will undoubtedly say—as well as highlight new chip products and the future of the circuitry that underlies them, a company spokesperson said.
That means Otellini is likely to add to details to Intels previously announced plans to accelerate the pace at which it introduces new processor architectures.
Otellini in April 2006 said that Intel would begin rolling out new architectures, which provide the circuitry of its PC and server chips, every two years in between shifts in manufacturing technologies.
Thus far, Intel has only unveiled the code names—Nehalem and Gesher—for its next two major changes.
But it has said that the new cadence has become necessary to meet its goals of boosting performance without increasing power consumption.
It will intersperse the architecture changes with manufacturing transitions, which generally make the features inside each ship smaller, allowing for larger numbers of transistors and thus performance to be added.
Intel is now using the extra transistors to create multicore chips.
After launching Core Microarchitecture earlier in 2006, Intel will orchestrate whats called a shrink by moving Core Microarchitecture to 45-nanometer manufacturing technology. The so-called shrink will be dubbed Penryn.
Then, during 2008, Intel will deliver Nehalem, a new chip architecture that follows Core Microarchitecture. It will mint Nehalem-architecture chips using the 45-naometer manufacturing process.
During 2009, Intel will move to 32-nanometer chip-making, rolling out a shrink it calls Nehalem-C. Gesher, yet another new chip architecture, will arrive in 2010, Intel has said.