Intel Corp. engineers on Thursday will announce a "breakthrough" aimed at minimizing this current leakage at the International Workshop on Gate Insulator 2003 in Tokyo.
The new improvements will be introduced into Intels lines when it begins manufacturing microprocessors with a 45-nanometer process, sometime in 2007, according to company officials. At that time, the use of a high-dielectric-constant (or high-k) material will help prevent battery packs from draining their charge when not being used.
Intels announcement of a solution to the leakage problem follows rival Transmeta Corp.s recent demonstrations of low-power processors. Transmeta designed its Crusoe chips to minimize power. The company last month disclosed LongRun2, a technology to minimize leakage current that combines hardware, software and an improved manufacturing process. LongRun2 is due out in mid-2004 and will be used in the Efficeon family of processors, according to Kenn Durrance, a spokesman for Transmeta.
However, Intels researchers have been working on the problem of current leakage for the past fifteen years, according to Ken David, director of components manufacturing for Intel. "We believe what were reporting is a significant breakthrough," he said.
The effects of leakage are apparent now, Intel researchers said, but will grow increasingly more important over time.
The problem, however, is fundamental to the transistor architecture of microprocessors, which incorporate sub-microscopic dielectric gates and plugs. As Intel manufactures chips on finer processes, the thickness of the gates shrink accordingly. Over time, more current can "leak" through the dielectric plug, David explained. At 90-nm, the next generation of chips, the gate dielectric will only be five atomic layers thick and will shrink even further over time.
Intels 2007 fix will be to replace the current gate insulation material, silicon dioxide, with an undisclosed "high-k" material. The new process will also require a new metal gate material to fabricate the other portions of the transistor. These will be laid out one atomic layer at a time, David said.
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