Justin Rattner, Intels chief financial officer, kicked off the companys spring Developer Forum here March 7 by taking the wraps off some of the features behind the chip makers Core Microarchitecture. Core Microarchitecture, otherwise known as Next Generation Microarchitecture, is a redesign of the circuitry that underpins Intels entire chip line. It not only delivers double-digit performance gains across desktops, notebooks and servers, but it will also help deliver double-digit cuts in power consumption, Rattner said. Intel first discussed it last August.
The main focus of the new architecture is cutting power consumption—a growing worry among businesses whose data centers are straining under increases in demand for electricity and cooling from deploying larger numbers of x86 servers and whose road warriors demand light laptops with longer battery life—while also increasing performance. Thus, the new architecture is, in some ways, paradoxical. Typically, bumping performance also involves making sacrifices in power.
"Energy is on everyones mind," Rattner said. However, "theres a fundamental tension here between performance and energy consumed. Its a classis trade-off. One, for example, that automotive designers have to deal with."
Using Detroit as an analogy, car makers can deliver models that offer tremendous acceleration and top speeds, but which use lots of gasoline, or cars that offer tremendous range, but whose performance is less exciting, Rattner said. However, Intel claims to have turned that formula on its ear with the new architectures.
"Core combines energy efficiency … with the same features that are expected in top-of-the-line microprocessors" such as virtualization, Rattner said. "Together, they deliver outstanding performance not just in mobile platform, where the technology originated, but across the entire range."
Thus, the first of three new Core Microarchitecture chips—Merom, Conroe and Woodcrest, dual-core chips for notebooks, desktops and servers, respectively, all of which are due later this year—will offer 20 to 40 percent increases in performance while cutting desktop and server power. Merom, for its part, offers a performance increase while holding the line on power.
Merom will offer a 20 percent performance boost versus todays Core Duo processors while operating within the same power envelope, Rattner said.
Conroe, a desktop chip due in the third quarter, will deliver a 40 percent improvement in performance with a 40 percent reduction in power. It will offer a 65-watt thermal design power measurement, Intel officials said.
Woodcrest, which will be of particular interest to IT managers, offers an 80 percent performance improvement, along with a 35 percent reduction in power relative to Intels current Xeon DP 2.8GHz dual-core chip for dual-processor servers, Rattner said.
Among the key elements of the architecture—and the heart of the reason Intel says it can deliver performance gains while cutting power—are features such as its ability to executive four instructions in a single clock.
"That has given us the ability to get more done in fewer cycles. By doing so we consume less power," Rattner said.
The Core Microarchitecture uses a 14-stage pipeline, a sort of assembly line for instructions that breaks them down in order to act on them in parallel, in addition to a more advanced cache that features improved access times, meaning processor cores arent waiting for data.
Pipeline length is an important element for chip performance and power. A longer pipeline allows a chip to hit higher clock speeds—although clock speed brings increases in power consumption—but performance gains dont always ensue. Longer pipeline chips take longer to recover from errors in later stages, something analysts call the pipeline tax.
Thus, chip makers must arrive at a balance. The Core Microarchitectures 14-stage pipeline is slightly longer than that of some chips, such as the Core Duo, which has 12. But its about half that of the Pentium 4, later versions of which had 31 stages. The Pentium 4, meanwhile, employed a complicated scheme that allowed it to process between one and three instructions per clock cycle.