Intels Dual-Core Chips Bump Next-Gen Pentium 4, Xeon
Intel Corp. is canceling the next generation of its desktop and server chips as it moves up its schedule for releasing processors with two cores on a single piece of silicon.
The Santa Clara, Calif., chip maker was scheduled to release its next-generation Pentium 4 chip, code-named Tejas, next year, as well as a Xeon processor targeted for low-end servers, code-named Jayhawk. Built on the same architecture as Tejas, that chip also was expected to be released in 2005.
However, given the work done by its engineers, Intel will be able to accelerate its schedule for releasing dual-core processors, making Tejas and Jayhawk unnecessary, said Intel spokesman Bill Kircos. Intel officials have been saying that a dual-core Itanium chip, code-named Montecito, will be released in mid-2005, followed by dual-core processors for desktops and mobile computers. The company has yet to release the code names for those chips.
Now Intel will have dual-core chips in its entire line of processors by the end of 2005, Kircos said. Given that, it made no sense to release Tejas and Jayhawk and expect customers to start standardizing on those processors if they were going to be quickly followed by the dual-core Pentium 4 and Xeon, he said.
The engineers working on Tejas and Jayhawk will be reassigned to the dual-core processor projects.
Dual-core processors enable users to get almost double the processing power in the same amount of space. IBM and Sun Microsystems Inc. have moved to dual-core processing in their RISC-based Power and SPARC architectures, respectively, with Intel making the move next year. Advanced Micro Devices Inc. will move to dual-core processing with its 64-bit Opteron server processor, most likely next year.
In an unrelated move, Intel on Monday will release three mobile chips in the next-generation family of its Pentium M processor, code-named Dothan. Pentium M is the processor in Intels Centrino wireless platform. Dothan will run at faster speeds than the current Banias model and will double the current 1MB of Level 2 cache.