IBM Touts Power5 Chip

 
 
By Jeffrey Burt  |  Posted 2003-10-14
 
 
 
Users of servers powered by IBMs upcoming Power5 processors will be able to perform routine maintenance without having to shut down the systems and will see performance improvements without having a bump in switching power.

Those will be among the new features discussed Tuesday when IBM officials take the stage at the Microprocessor Forum in San Jose, Calif., to talk about the chip, which is scheduled to launch in mid-2004.

The new chip is designed to build off the enhancements that were put into the current Power4 and Power4+ chips, including logical partitioning, on-demand capacity upgrading and chip kill memory. The features in the Power5—which will be binary and structurally compatible with the Power4 and 4+—will go further in reducing costs and complexity for users, said Joel Tendler, program director for technology assessment at IBM.

"Technology can get to the point where, if left unbridled, it becomes complex, and thats the wrong way," Tendler said.

Some of features IBM already has discussed over the past few months, including simultaneous multi-threading capabilities—outlined at the Hot Chips conference in August—which officials with the Armonk, N.Y., company say will increase performance by 40 percent over the Power4 by enabling the processor to operate on more than one instruction thread at a time.

In addition, Power5—which will be installed in both the eServer p and iSeries—will bring dynamic partitioning into the sub-CPU level. With a 64-way server powered by Power5 chips, "we can make it look to software like we have 1,200 processors," Tendler said.

New firmware upgrades will enable administrators to perform routine system maintenance without having to shut down the server, Tendler said. Currently, with Power4 systems, that can only happen with unscheduled outages, he said.

"This will significantly reduce the number of scheduled outages," Tendler said.

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