Intel Execs Talk Xeon Phi at Supercomputing Show
The upcoming "Knights Landing" chip will bring significant improvements in performance, memory and interconnect, Intel officials said.Intel's upcoming version of its Xeon Phi technology will be a key step in the push toward more widespread adoption of high-performance computing and toward the eventual goal of exascale computing by the end of the decade, according to company officials. Speaking at the SC '13 supercomputing show in Denver Nov. 19, Intel officials said the "Knights Landing" version of the Xeon Phi chip will bring with it significant improvements in both performance and power consumption, not only though its 14-nanometer manufacturing process but also via its ability to be used as either a primary compute processor or as a coprocessor in conjunction with another host processor, such as Intel's Xeon server chips. Knights Landing will be a key departure from the current 22nm Xeon Phi coprocessors and the GPU accelerators being offered by Nvidia and Advanced Micro Devices, all of which are designed to help ramp up the performance of high-performance computing (HPC) systems without increasing the amount of power they consume, officials said. Knights Landing will have many cores (the current coprocessors offer as many as 60), will be able to run single-threaded and parallel-processing applications, will offer greater integrated on-package memory capabilities and improved interconnect and—as a host processor—will not have to wait for applications to pass through a primary processor, as coprocessors and GPU accelerators have to today, according to Joe Curley, director of marketing for Intel's Technical Computing Group.
"It will be a processor and will be able to be used as a coprocessor," Curley told eWEEK in an interview before the start of the SC '13 conference.