Intel Gives Glimpse of Upcoming Next-Gen Xeon Phi

 
 
By Jeffrey Burt  |  Posted 2013-06-17 Email Print this article Print
 
 
 
 
 
 
 

Intel officials at the ISC said the 14nm Knights Landing will be able to play both the processor and coprocessor roles in HPC environments.

Intel officials, seven months after introducing the company's Xeon Phi coprocessors for high-performance computing systems, are highlighting the technology's success while giving the industry a glimpse of what will come in the next generation, called "Knights Landing."

At the same time, the company is expanding the current Xeon Phi portfolio with two new product lines that are designed to give organizations a greater range of choices depending on workload, cost and performance.

The overall thrust of Intel's message this week at the 2013 International Supercomputing Conference (ISC) in Germany is that the Xeon Phi coprocessors, more than competing graphics accelerators from Nvidia and Advanced Micro Devices, are the better option for high-performance computing (HPC) environments.

"This will be a fundamental accelerator … of high-performance computing going forward," Rajeeb Hazra, vice president and general manager of Intel's Technical Computing Group, told journalists on a conference call a few days before the ISC opened.

Nvidia and AMD for the past few years have championed their GPU accelerators as the products needed for organizations that want to ramp up the performance of their supercomputers while keeping their power consumption in check. The systems can offload more highly parallel workloads from the main processor to the accelerators—which are smaller and offer many more cores than primary processors—freeing up the bigger and less energy-efficient base processor to work on the more compute-intensive tasks.

Intel a couple of years ago began working on its Many Integrated Core (MIC) initiative, which resulted in the Xeon Phi, a coprocessor that offers more than 60 cores to essentially do the same job as the GPU accelerators. The key is that—like Intel's Xeon processors and AMD's Opteron server chips—the coprocessors are built on the x86 architecture.

Intel officials argue that most programmers already are familiar with the x86 architecture and its tools, so working with Xeon Phi will be easier. Workloads running on Xeon Phi coprocessors have to undergo less recoding than those running on GPU accelerators, they said.

It's the key point Hazra and other Intel officials at the ISC are making in their argument for what they call "neo-heterogeneity." HPC environments are going to be heterogeneous, with the use of both processors and coprocessors or accelerators, Hazra said. With Xeon Phi, Intel offers heterogeneity in hardware, but with a common programming model.

Officials for both AMD and Nvidia have countered that the amount of recoding for GPU accelerators is minimal and not a real obstacle to their use, and have said they are not done innovating their products.

The massive Tianhe-2 supercomputer in China—also called Milky Way-2—which now tops the Top500 list as the fastest system in the world, uses 32,000 Xeon E5-2600 processors and 48,000 Xeon Phi coprocessors. In addition, the sixth-fastest system, the Dell PowerEdge-based Stampede at the Texas Advanced Computing Center, also leverages Xeon Phi coprocessors.

 



 
 
 
 
 
 
 
 
 
 
 
 
 

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