Intel Intros First Xeon Phi Coprocessors for HPC Environments

 
 
By Jeffrey Burt  |  Posted 2012-11-12 Email Print this article Print
 
 
 
 
 
 
 

At the SC12 show, the giant chip maker announces that the first of the new chips made for supercomputers will be ready in January.

Intel has begun shipping the first of its Xeon Phi coprocessors to systems makers as it looks to improve performance and drive down power consumption in supercomputers used for scientific research.

Intel engineers for several years have been working on what had been called the “Knights Corner” chips as part of the company’s Many Integrated Core (MIC) project, which aims to create coprocessors that will enable supercomputers to handle scientific workloads—particularly those that are highly parallel in nature—faster and more efficiently.

At the SC12 supercomputer show in Salt Lake City on Nov. 12, the giant chip maker announced the Xeon Phi 3100, which will offer more than 60 cores and will be available in systems in the first half of 2013. The coprocessor, which will offer more than a teraflop of peak double-precision performance, will be aimed at compute-intensive, parallel workloads in such areas as life sciences, financial services and oil exploration.

There will be two versions of the 3100—the Xeon Phi 3100A will come with a cooling fan of its own; the 3100T won’t, instead using the fan in the supercomputer.

In addition, Intel’s Xeon Phi 5110P will be generally available Jan. 28, 2013, and also will offer more than a terabyte of double-precision peak performance. It will be aimed at tasks that are more memory-intensive. It will start at $2,649.

The chips are built using Intel’s 22-nanometer manufacturing process, and includes the 3D Tri-Gate transistors, which were introduced with the “Ivy Bridge” chips.

High-performance computing (HPC) organizations—from such areas as scientific research into climate change and medical imaging to industries such as pharmaceuticals and financial service to national security agencies—have been pushing for supercomputers that offer greater performance while keeping power consumption low. Systems makers over the past few years have turned to accelerators, including GPU accelerators from the likes of Nvidia and Advanced Micro Devices, which work with CPUs to boost compute power while remaining energy efficient.

At the SC12 show, both Nvidia (with its Tesla K20 GPU) and AMD (with its FirePro S10000 GPU) unveiled new accelerators Nov. 12.

Intel officials are looking to Xeon Phi coprocessors to do the same job, but argue that given that they’re based on the x86 architecture, they offer advantages over GPUs, such as supporting common x86 tools that organizations are familiar with.

The Xeon Phi coprocessors already have made an impact. The Stampede supercomputer at the Texas Advanced Computer Center, in Austin, runs Dell servers powered by Intel’s eight-core Xeon E5 processors. It also is the first system to feature the Xeon Phi coprocessors, and is ranked as the seventh-fastest supercomputer in the world, according to the latest Top500 list of the fastest systems, released at the SC12 show Nov. 12.

Included in Stampede are two versions of the Xeon Phi coprocessors—the SP10E and SP10C—each of which holds 61 cores and which were built specifically for the supercomputer, which currently has a performance of 2.6 petaflops, but will top out at 10 petaflops when it’s all built out.

In addition, Xeon Phi coprocessors are in six other systems on the Top500 list, according to Intel.

Intel engineers have been working on the company’s MIC project for eight years, building on the work from its Larrabee project, which ended in 2009. Company executives have been talking about it for the past couple of years, and at the SC11 show in Seattle in 2011, Intel engineers showed off the first working samples.

“A great deal of [effort] went into this technology,” John Hengeveld, HPC segment marketing director for Intel’s Technical Computing Group, said during a recent workshop at TACC. “This is a new era of computing.”

The Xeon Phi coprocessors are a key part of Intel’s larger effort to reach the exascale level of computing by 2018. The coprocessors, combined with Intel’s Xeon CPUs, over the next few years will enable supercomputers to hit performance levels to reach the exaflop goal while maintaining high energy efficiency, according to company officials.

 More than 50 OEMs—including Acer, bull, Cray, Dell, Fujitsu, Hewlett-Packard, IBM, NEC and SGI—are creating systems that leverage the Xeon Phi coprocessors, according to Intel.

 
 
 
 
 
 
 
 
 
 
 
 
 

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