The "ORNAND" flash, scheduled for an introduction in 2005, will allow AMD to break out of its niche in the NOR flash market—which it shares with Intel Corp.—and compete in the market for flash memory cards. AMD executives disclosed the technology as part of the companys fall analyst meeting Friday at its headquarters here.
With ORNAND, AMD hopes to attach a NAND interface to a NOR chip, allowing popular small-form-factor storage media, such as Secure Digital cards, to be created with AMDs memory.
Bertrand Cambou, chief executive of AMDs Spansion LLC flash-memory joint venture with Fujitsu Ltd., said the company has been in talks with several of the small-form-factor flash card organizations, including the MMC (MultiMedia Card) coalition.
"Our engineers have essentially architected a new invention which we believe can bring about a new revolution," Cambou said. The combination of NOR flash and the NAND interface is "the best of both worlds," he said, and will be pin-compatible with NAND solutions.
Once the technology ramps up, ORNAND will be a "disruptive technology," added Hector Ruiz, AMDs chairman, chief executive and president.
Although AMD is typically seen as a microprocessor company, its flash revenues have equaled or in some periods even surpassed the revenue it received from its microprocessor business. But the market in which it competes, NOR flash, has been a two-horse race between it and rival Intel, with AMD winning.
With ORNAND, AMD will now be competing in a far more punishing market: AMD and Intel rank third and fourth in overall flash memory production behind Samsung Electronics and Toshiba Ltd., respectively.
NOR flash was originally designed for code storage, the programs and applications used by cell phones and PDAs. As the need for mobile storage has grown, however, demand has also increased for NAND storage, used to store data. NAND costs less per bit than NOR flash and is of higher density. The downside, however, is that NAND is perceived as less reliable than NOR flash.
Since flash memory constantly flirts with commodity status, pricing will be the most effective lever to position ORNAND against traditional NAND flash, analysts said.
That means AMD must be able to effectively manufacture the chip through a cost-effective manufacturing process, which it will achieve by moving to larger wafers, shrinking its manufacturing process and increasing its output. The end goal is to dilute the manufacturing costs further and further, allowing the company to keep lowering prices while turning a profit.
To do that, the Spansion venture intends to convert its 200-mm wafer fab JV3 fab in Aizu-Wakamatsu, Japan, to a larger facility eventually capable of producing 300-mm wafers at 65-nm linewidths and beyond, Cambou said.
The JV3 fab currently has a portion, dubbed "SP1," dedicated to 200-mm production lines that will be converted over the next few years to a single, 250,000-square-foot clean room capable of 60,000 wafers per month, Cambou said.
Although AMD plans to hold its 2004 and 2005 capital equipment costs stable at $1.5 billion, about $100 million will be diverted to Spansion in 2005 to begin funding the expansion, AMD chief financial officer Bob Rivet said.
The larger wafer size will allow more flash chips to be produced, amortizing the fixed manufacturing cost over a larger number of chips. In addition, Cambou pledged to reach the 65-nm manufacturing node by early 2007, the same time table that both Samsung and Toshiba have publicly stated.