IBM Rolls Out Power5 Chip

Transmeta betting its future on Efficeon.

Industry stalwart IBM and upstart Transmeta Corp. presented a picture in contrasts at the Microprocessor Forum in San Jose, Calif., this month.

As IBM officials outlined the features of their upcoming Power5 chip, the key to the Armonk, N.Y., companys Unix strategy, Transmeta rolled out its newest processor, the Efficeon, upon which it is betting its future.

The Power5, due in mid-2004, will build off enhancements that were incorporated into the Power4 and Power4+ processors, such as logical partitioning, on-demand capacity upgrading and chip kill memory. The features of the Power5—which will be structurally and binary-compatible with IBMs Power4 and 4+ predecessors—will go further in reducing costs and complexity for users, officials said.

Earlier in the year, IBM officials talked about some of the upcoming enhancements, including simultaneous multithreading, which they said will lead to a performance improvement over the Power4 of as much as 40 percent. As with the Power4, the new chip will have two cores on a single piece of silicon, but each core will be able to run two threads—or instructions—at the same time. Administrators also will be able to turn off the multithreading capability.

The Power5 will appear in IBMs eServer pSeries and iSeries systems.

Brendan Carlton, systems manager for packaging company Huhtamaki Americas, which runs iSeries servers, said the new firmware upgrades will result in less downtime for his systems.

"Any changes to technology that [allow] someone like myself to apply fixes without having to perform a reboot or take the system offline is a major plus," said Carlton, in De Soto, Kan. "The folks I support are running in a true seven-days-a-week, 24-hours-a-day operation within a just-in-time supply-and-manufacturing environment. Even a simple 15-minute reboot to apply fixes to the OS or system can cause our planners serious problems and backlogs."

Transmeta, of Santa Clara, Calif., released its long-awaited Efficeon chip, also known as the TM8000, as it tries to push back into mainstream computing. The chip—which will run at speeds between 1GHz and 1.3GHz—is targeted at devices that use Transmetas energy-efficient Crusoe chips, such as thin-and-light notebooks. Officials said they hope it will enable Transmeta technology to move up the food chain into traditional notebooks and blade servers.

Along with the chip— which will come in three versions—Transmeta unveiled LongRun2, technology that will enable the processors internal x86 code-morphing software to reduce current leakage, which wastes power when the chip is not being used.

The old and the new

IBM and Transmeta tout their upcoming chips
  • IBMs Power5 includes simultaneous multithreading; dynamic partitioning at a sub-CPU level; firmware upgrades, for easier maintenance; and Dynamic Power Management, for better energy efficiency
  • Transmetas Efficeon runs at speeds from 1GHz to 1.3GHz, with a second generation set for next year, with speeds ranging up to 2GHz; LongRun2 manages current leakage