64-Bit CPUs: What You Need to Know - Page 10

IA-64 is surprisingly stingy with memory-addressing modes. It has precisely one: register-indirect with optional post-increment. This seems horribly limiting but is very RISC-like in philosophy. Addresses are calculated just like any other number and deposited in a general-purpose register. By avoiding special addressing modes, Itanium avoids specialized hardware in the critical path. VLIW pushes complexity onto the compiler instead of the hardware.

Loads can be pretty uninteresting, but IA-64 manages to spice them up a bit. Loads can "hint" to the cache that it would be beneficial to preload additional data after the load, whether that data is likely to be reused, and if so, which of the three cache levels is most appropriate to hold it. These are not the kinds of things even dedicated assembly-language programmers are likely to know, but large-scale commercial developers might profile a new operating system or major application extensively, and use the feedback to provide prefetch and caching hints. These are just hints, too--the processor is under no obligation to act on the hints or the caching information.