64-Bit CPUs: What You Need to Know - Page 11

Somewhat stronger than a hint is a speculative load, an instruction that tells the processor it might want to load data from memory. Programmers (or more realistically, advanced compilers) can sprinkle their code with speculative loads to try to snag data that might be needed soon. Itanium will do its best to comply, but if the system bus is busy, the speculative load might be postponed indefinitely. If a speculative load fails (such as from a memory fault or violation) the processor does not raise an exception. Hey, it was only speculative anyway.

Itanium can hoist loads above branches, which many high-end RISCs do, but it can also hoist loads above stores, which is much trickier. The usual problem with the latter procedure is alias detection: the compiler cant be sure that loads and stores arent to the same address. As long as theres a chance, its dangerous to load from memory before all the stores to the same memory addresses are finished. Yet loads are time-consuming, so its a big win if you can accelerate them.

IA-64 gets around this problem--with a little help from you--with the LD.A (load advanced) instruction. LD.A speculatively loads from memory, but also stuffs the load address into a special buffer called the Advanced Load Address Table (ALAT). Subsequent stores to memory are checked against addresses in the ALAT. If theres a match, the speculative load aborts (or, if it already completed, the contents are discarded). Using the data from a LD.A can be tricky, too. You need to validate them with a CHK.A instruction first. Theres no guarantee that any calculations you did wont have to be redone with valid data. Its a bit of a gamble, but can pay handsomely if you speculate wisely. Architecture imitates life.