Beast: A Modified VLIW Core">
Internally, Itanium is a six-issue processor, meaning it can profitably handle six instructions simultaneously. Its also a VLIW (very long instruction word) machine with some enhancements for added flexibility in instruction groupings, less code expansion than classic VLIW designs, and better scalability, to permit wider parallel instruction issue in future IA-64 processors. Thus Intel prefers the term EPIC: Explicitly Parallel Instruction-set Computing.
Itanium has nine execution units and future IA-64 processors will probably have more. The nine are grouped into two integer units, two combo integer-and-load/store units, two floating-point units, and three branch units. These four groups are significant, as we shall see in a moment.
Heres a simplified Itanium block diagram:
And heres a more complex block diagram:
Itanium has a 10-stage pipeline, which is respectable but not impressive by todays standards. Again, future IA-64 processors may have different and probably longer pipes. For comparison, Pentium III has a 12-stage pipeline, but the Alpha 21264 has just eight stages. And Pentium 4 has 20 stages (from the point of fetching micro-ops from its trace cache), and Athlon has 10 stages.
Heres a basic Itanium pipeline diagram: