AMD Lays Out the Argument for Zen at Hot Chips Show

By Jeffrey Burt  |  Posted 2016-08-23 Print this article Print
AMD chips

Company engineers outline the myriad innovations in the new CPU microarchitecture that are driving the performance and efficiency improvements in its Zen core.

Officials with Advanced Micro Devices went to the Hot Chips 2016 show to preach the benefits of "Zen."

Company executives last week were in San Francisco at a hotel not too far from where larger rival Intel was holding its annual developer conference to demonstrate the new Zen microarchitecture, which will form the basis of future processors that will power everything from fanless notebooks to supercomputers for high-performance computing (HPC) environments.

AMD is expecting the Zen core, which is slated to begin appearing in high-end desktop PCs later this year and into 2017 and in servers in the second quarter, to fuel its push to become competitive again in the client and data center spaces. President and CEO Lisa Su and other executives introduced Zen in May 2015 as the cornerstone of the company's restructured product road map, and now have begun to show the industry what the new microarchitecture can offer in terms of performance and power efficiency.

That brought Mike Clark, senior fellow at AMD, to Hot Chips in Cupertino, California, Aug. 23 to outline what company engineers did to build the new microarchitecture, which now delivers 40 percent better instructions-per-clock performance over the company's current Excavator core while keeping a lid on power consumption.

In an interview with eWEEK before the presentation, Clark and Sam Naffziger, AMD corporate fellow, talked about the challenges presented to them and other engineers four years ago when they were tasked with overhauling the AMD microarchitecture to create a core that will enable the company to once again compete in an increasingly crowded processor space. Not only did that space include traditional rival Intel, but also newer competitors in ARM and its array of manufacturing partners such as Qualcomm and Samsung, not to mention a revived IBM and its new OpenPower effort.

The key from the beginning was achieving the performance gains while keeping power consumption down, Clark said. With Zen, energy efficiency was going to be just as important as performance.

"We had to reset the architecture," he said. "We focused on the power of the architecture from the beginning."

With Zen, AMD officials are hoping to make the same sort of impact on the market that the company made more than a decade ago, when it was the first vendor to offer 64-bit computing in the x86 architecture and then dual-core processors. The innovations enabled AMD to capture about a quarter of the server market, but Intel's design and manufacturing prowess, combined with missteps by AMD, conspired to knock away at the market share. Intel now sells more than 90 percent of all server chips worldwide.

Such microarchitectures as "Bulldozer" and "Excavator" were disappointments, and AMD officials decided that what the company needed was a complete reworking of the core design. Naffziger said that AMD for several years had been able to depend on innovation in such areas as GPUs and systems-on-a-chip (SoCs) to keep moving forward, even with cores that he said were "not as competitive." With the advancements in Zen, that problem has been solved.

"Now we are getting the final element that we had been missing in a very competitive core," Naffziger told eWEEK.

The Zen cores come with a broad range of enhancements that target both performance and power efficiency, including running two threads per core, a large operational cache, faster Layer 2 and L3 cache and improved L1 and L2 prefetcher. Engineers also reworked the CPU's cache, essentially building a bigger engine, Clark said. Zen offers almost twice the bandwidth in the L1 and L2 cache than Excavator and up to five times the bandwidth for the L3 cache.

AMD also embraced simultaneous multithreading—a technology similar to Intel's Hyper-Threading—for improved performance and improved the branch prediction technology. It used a 14nm FinFET manufacturing process for better performance and efficiency.


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