AMD Developing 32-Core Zen APU for Supercomputers
The chip maker unveiled some details of its upcoming Exascale Heterogeneous Processor in a paper submitted to the IEEE.Advanced Micro Devices reportedly is developing a high-end chip aimed at supercomputers that will include as many as 32 "Zen" processing cores and an unknown number of its upcoming "Greenland" GPUs. Some of the details of AMD's "Exascale Heterogeneous Processor" (EHP) were outlined in a paper submitted to IEEE (Institute of Electrical and Electronics Engineers) and first published in the Bits and Chips news site. According to the site, the new accelerated processing unit (APU) could hit the market between 2016 and 2017. The new EHP would fit in with AMD's larger plans to make an aggressive push back into the data center. At a meeting with financial analysts and journalists in May in New York City, President and CEO Lisa Su and other executives said the recharged effort in the data center would include not only servers, but also workstations, networking gear and storage products. Su said the data center "is probably the biggest single bet we're making today." However, the executives said the growing demand for more choice in the x86 server market was due to the need for more competition and to improve the economics and innovation in the space. AMD wants to provide that alternative to Intel, according to Forrest Norrod, senior vice president and general manager of the company's Enterprise, Embedded and Semi-Custom Unit.
Not surprisingly, AMD is taking a heterogeneous approach to the idea of a chip for exascale computing. Since buying graphics maker ATI in 2006, the vendor has been at the forefront of integrating its CPUs and GPUs on the same piece of silicon—creating its APUs—and along with Nvidia has been aggressive in pushing GPU accelerators to help organizations in the high-performance computing (HPC) space speed up the performance of their supercomputers while holding down power consumption. The GPUs can more efficiently run the highly parallel workloads that are becoming more commonplace in HPC.