eWEEK content and product recommendations are editorially independent. We may make money when you click on links to our partners. Learn More.
While some would have us believe that computer hardware at its core is no more than a race to commoditization—best exemplified by the prevalence of industry-standard, high-volume microprocessors—a visit to the recent Microprocessor Forum in San Jose, Calif., offered abundant proof otherwise.
The maker of the largest family of industry-standard microprocessors, Intel, chose not to attend, but plenty of other chip makers were present. What they had to show was encouraging for the future of innovation and the future relevance of IT to corporate strategy.
One of the most striking developments was in security, where Centaur Technology devised a different—possibly better—idea than the NGSCB (Next- Generation Secure Computing Base) plan, formerly called LaGrande-Palladium, cooked up by Microsoft and Intel.
Glenn Henry, Centaurs president, revealed that basic security operations have been added to his companys x86-compatible microprocessors. The idea, said Henry, is similar to that of three-dimensional graphics—another computationally intensive capability once thought too specialized to put into general-purpose processors but that is now widespread.
Centaur makes random-number generation and AES encryption available in a high-speed, properly tested form that lets developers build the security they need around applications. Its easy to implement those key functions incorrectly in software. And in contrast to NGSCB, the Centaur approach does not entirely lock up the system; Centaur provides reliable security components, instead of imposing NGSCBs one-size-fits-all model, which unduly constrains users as the price of protecting content owners.
Centaur is not alone. Last week, ARM announced new licensable cores that take a different route toward security using TrustZone architecture. Going beyond the supervisor-privilege model of a conventional microprocessor, ARMs approach extends to the memory system to make cache contents and other potential targets of attack as secure as the data and the control flows of the processor core.
This looks like the difference between the old approach to computer design— make it unlikely to break by accident or carelessness—and the needed future approach: making things hard to break despite patient, savvy intent. With security flaws rampant, the logic of putting security algorithms in hardware is unassailable. Its faster, more consistent and in the volume todays network-based environment makes inevitable, destined to be much less costly. Whats more, it looks as if there will be multiple approaches to doing it, ensuring strong competition. Centaurs and ARMs innovations will be on the market next year. Microprocessor competition and innovation are alive and well in security, where they are needed most.
Send your comments to eWEEK@ziffdavis.com.
