eWEEK content and product recommendations are editorially independent. We may make money when you click on links to our partners. Learn More.
SEATTLE – A standards group made up of the leading IT vendors today will roll out the first draft of a new interconnect specification for linking microprocessors and peripherals.
The first draft of the Third Generation I/O spec, known as 3GIO, has been completed and is being transferred to the PCI-SIG, where it will be renamed PCI Express, the group will announce today at the Windows Hardware Engineering conference here.
PCI Express is a new serial I/O technology, compatible with the current PCI software envi-ronment, that defines a packetized protocol and a load/store architecture. Its layered architecture enables attachment to copper, optical, or emerging physical signaling media.
PCI Express uses an embedded clocking scheme to enable better frequency scaling and pro-vides many advanced features as well as innovative form factors, according to people familiar with the specification. It can be used for chip-to-chip and add-in card applications to provide connec-tivity for adapter cards, as a graphics I/O attach point for increased graphics bandwidth, and as an attach point to other interconnects like 1394b, USB 2.0, InfiniBand Architecture and Ethernet.
PCI-SIG is the industry organization that owns and manages the PCI Local Bus specifica-tion as an open industry standard. The organization defines and implements new industry stan-dard I/O (input/output) specifications as local I/O needs evolve.
Roger Tipley, the president and chairman of the PCI-SIG, said the PCI Express name re-flected the high-speed, point-to-point qualities of the new local bus architecture, emphasizing that software compatibility was maintained between PCI and PCI Express.
The PCI Express draft specification is currently under review by the PCI-SIG board. Once approved, the specification will be sent to the PCI-SIG membership for a 60-day review, with the final public release of the PCI Express 1.0 specification expected in the second quarter of 2002.
The delivery of the specification is the result of a working relationship combining the tech-nical expertise of the Arapahoe Work Group. It consists of representatives from Compaq Computer Corp., Dell Computer Corp., Hewlett-Packard Co., IBM, Intel Corp. and Microsoft Corp.
“Thanks to the thorough efforts of the Arapahoe Work Group, this new serial interconnect draft specification is being delivered to the PCI-SIG in a comprehensive and mature form, with scalable performance that fully lives up to its new name,” Tipley said.
Rob Short, a vice president of Microsofts Windows division said the Redmond, Wash., software firm viewed PCI Express as an exciting technology for the I/O bandwidth and scalability that it brought to both the computing and communications industry, as well as the opportunities it would provide for system and device manufacturers to expand beyond the form factor and I/O ex-pansion boundaries imposed by the current I/O architectures.
“Microsoft will support PCI Express in the PCI-SIG at the board of directors level and with active participation in the SIG workgroups,” Short said.
Louis Burns, a vice president and co-general Manage of Intels Desktop Platforms Group, said PCI had been one of the most successful I/O initiatives in the industry. “We now have a com-pelling opportunity with PCI Express, as the next generation of PCI, for continued innovation and performance enhancements in both computing and communications platforms,” Burns said.
Peter Hortensius, a vice president of development for IBM Personal Computing Devices welcomed the move, saying IBM recognized the value of industry standards in the evolution of PC architecture.