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Advanced Micro Devices will pull back the curtain a little more on its first quad-core processor the week of Feb. 12.
At the International Solid State Circuits Conference in San Francisco, which kicks off Feb. 11, the companys engineers will demonstrate new technology that will make AMDs first quad-core chip more power-efficient than previous dual-core processors.
The quad-core AMD Opteron processor, which goes by the codename “Barcelona,” is scheduled to be released later this year. It will compete against Intels quad-core Xeon 5300 series, which the company released last November.
AMD, which is based in Sunnyvale, Calif., believes that its engineers have developed a better, “native” quad-core design, which allows four, x86 processing cores on a single piece of silicon. By comparison, Intels quad-core processor ties two dual-core chips onto a single piece of silicon.
In addition, Intel and AMD have each poured money and resources into technologies that ease the power consumption and heat generation of their processors.
At this weeks conference, AMD will show its quad-core processors power efficiency. Specifically, engineers have improved on the companys PowerNow technology, which can increase or reduce the amount of power to the chip depending on the demand.
This technology allows the chip to throttle back the power when the demand is low, which saves energy.
With the quad-core Opteron, the operating system, either Microsoft Windows or Linux, will direct the processor to pass information along through standard protocols, but the OS can also instruct the cores to adjust their power frequency depending on the workload, said Brent Kerby, AMDs Opteron product manager.
“If Core Zero is working a 80 percent utilization, but Cores 1, 2 and 3, are not very busy, they can lower their power frequency down, and then the cores can jump back up to take on a workload as needed,” Kerby explained.
Unlike dual-core chips, where the cores are interdependent on each other in terms of power consumption, the quad-core model with the OS allows all four cores to act independently.
“The OS can talk directly to the CPU and it can adjust the performance per core at the more opportunistic time and those change can then have less of an impact,” Kerby said.
In addition, AMD engineers will also demonstrate a feature in Barcelona that allows the four cores to be powered down independent of the system memory interface. This, according to AMD, will still allow peak memory performance, while saving on power.
The memory interface will also allow the read/write memory to power down. The result, AMD said, will allow a power savings of 80 percent with the memory controller.
Lastly, the power saving technology in the Barcelona chip will save on power by using so-called “fine” and “course” clock gaters, which shuts down finer sections of the core logic, resulting in additional power savings.
Kerby said that much of Barcelonas power-saving capabilities can be traced back to the AMDs Direct Connect Architecture, which allows improved memory and bandwidth in the chip by directly connecting memory and I/O to the CPU. It also allows the direct connection of CPUs to one another.
The “native” design of the quad-core also helps.
“When its all integrated into one piece of silicon, the architecture is very cohesive and all the parts work well together, which allow us to be innovative with some of these power savings capabilities,” Kerby said.
When Barcelona is released, it will be manufactured on a 65-nanometer process and will be built with either a 68-, 95- or 120-watt thermal envelope, which will also help reduce power costs.
So far, AMD officials have not given a firm date for the launch of Barcelona, but a spokeswoman said that the company will continue offering glimpses of its architecture and technology in the weeks leading up to the official release date.
