Advanced Micro Devices is diversifying its chip design efforts.
The chip maker will deliver two new chip architectures in 2007, changing the circuitry that underlies its server and desktop chips as well as its notebook and emerging market processors in order to better tune the chips for their respective markets.
It will also begin efforts to improve PC management, change the way client computers are designed, and foster broader development of co-processors for boosting the performance of specific functions on PCs and servers, with projects code-named Torrenza, Trinity and Raiden.
The diversification reflects AMDs recent growth, as well as the companys aggressive outlook and plans to keep growing.
As part of its strategy, the company also plans to bolster its manufacturing capabilities to allow it to serve up to a third of the chip market by 2008. Although not all x86 chips are used in PCs—some are used in set-tops and other consumer electronics, for example—IDC estimates show that the worldwide PC market, by itself, will top 250 million PCs by that time.
“Were going to give the commercial customer choice like theyve never had before with Raiden,” said Mary Seyer, senior vice president of AMDs Commercial Business Segment, during its annual analyst meeting in Sunnyvale, Calif., on June 1. “We think these three announcements today really set us apart in the industry. Where the competition was trying to chase us on one spectrum, weve reset and raised the bar.”
With new processors in the works and efforts to encourage the use of co-processors under way, AMD is seeking to diversify and carve out new markets, Seyer and other executives said at the analyst meeting.
To that end, it will use the two new chip architectures to develop performance-optimized quad-core Opteron server chips and either quad- or dual-core desktop processors. At the same time, it will use its second new architecture to develop dual-core notebook chips that offer reduced power consumption along with improved performance.
AMD said it will also use the lower-power architecture to deliver chips for computer gear aimed at emerging markets. There it has been working with Microsoft on “FlexGo,” or pay-as-you-go, computers and participating in the One Laptop per Child program, in addition to delivering its Personal Internet Communicator, an inexpensive Internet access device.
AMDs forthcoming chips may sprout from a new architecture. But the chips will continue the companys familiar strategy of integrating a memory controller, which handles the flow of data to and from system memory, and using the HyperTransport protocol as a pipeline for that data.
AMD, under a program code-named Torrenza, will open its platform architecture by allowing other chip makers to use its HyperTransport design and its chip sockets to build accelerators manufacturers can use to increase performance for specific jobs.
“We want to do a couple of things for the industry, here, that set this platform apart but allow the industry to innovate further,” Seyer said. “Now its not just AMD competing, its the entire ecosystem joining us to compete with Intel.”
In order to streamline design, AMD aims to make its new chips more modular, allowing it to reuse as much of its design work as possible, chip to chip and generation to generation, executives said.
Chip sets generally manage the flow of data inside a computer. However, AMD also sees the possibility for them to eventually perform new duties such as co-processing for TCP/IP—one potential path of evolution for its co-processor strategy.
AMD will pair all of its new chips with more advanced manufacturing, including a 65-nanometer manufacturing process and later a move to 45-nanometers.
The company plans to begin minting chips with its 65-nanometer process in volume during the fourth quarter of 2006. It plans to follow this with 45-nanometer production roughly 18 months later, in 2008, and less than two years after that with a 32-nanoamter process. The changes will give AMD access to many more transistors. Those extra transistors could be used for numerous jobs, including building larger onboard memory stores and building additional processor cores into its multicore chips.
AMD will gear its quad-core chips toward performance and power efficiency. To that end it designed each individual core in its forthcoming quad-core Opteron to get more work done per clock cycle, yet use less power, the company said.
The chip, which is designed to fit into the same power consumption levels as AMDs current dual-core Opterons, will feature the retuned processor cores, as well as extra onboard cache and the addition of a higher-bandwidth version of the HyperTransport interconnect, AMD said on May 16.
AMD also beefed up the floating-point units, generally used for number-crunching and multimedia-extension processing capabilities associated with the cores, and added a shared Level 3 cache—an extra pool of memory used to store data close to the processor cores—to help feed data into the cores individual Level 2 caches. AMD executives said the new Opterons would feature 2MB of L3 cache.
When it comes to power management, the Opteron chip will be able to power down its four cores independently. It could run one and power down three, for example, to reduce electricity consumption. Forthcoming notebook chips will have even finer levels of control: Two cores will be able to power down independently, as will the chips memory controllers and HyperTransport links, AMD executives said.
AMD also plans to beef up its computer platform-level work, the company said. For servers, the company will offer an eight-socket server platform design capable of enabling the combination of up to eight four-core processors for a total of 32 processor cores in one server.
Editors Note: This story was updated to include more information about AMDs plans as well as comments from AMD executives.