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    Micron Launches Phase-Change Memory for Mobile Devices

    By
    Chris Preimesberger
    -
    July 20, 2012
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      Is phase-change memory, acronymed PCM and discussed for the last six years as a potential replacement for NAND flash, finally ready for prime time?

      Solid-state semiconductor maker Micron Technology July 17 claimed to be the first in the industry to make available high volumes of its 45-nanometer phase-change memory chip for mobile devices. The Boise, Idaho-based company’s 45nm PCMs are targeted for high-end feature-type phones, with its longer-range strategy to build them for smartphones and tablet PCs.

      The new processors (wafer pictured at left) feature 1G-bit PCM plus 512M-bit LPDDR2 (Low Power Double Data Rate memory, also known as Mobile DDR, or MDDR) in a multichip package.

      Micron and its Numonyx division — which Micron acquired in 2010 for $1.27 billion — are key suppliers of PCM to IBM, which also is well-invested in this research and development for its own processors. IBM last noted some advancement in the technology in 2011. Intel is also among the top companies working on producing this hardware.

      PCM technology refers to silicon chips that can store multiple bits of data per cell over time without the data becoming corrupted. This is a problem that has been nagging development since IBM started this project nearly 10 years ago.

      Previously, each PCM cell was able to hold a single data bit, and even those became lost or corrupt at unpredictable times. The latest development updates can lead to solid-state chips that can store as much data as NAND flash disks (which now are up to 1TB-plus in capacity) but feature about 100 times the data movement speed, to go with a much longer life span.

      NAND Flash’s Inherent Cycle Limitations

      NAND flash is inherently slowed down by so-called erase-write cycle limitations. This is because NAND flash requires that data first be marked for deletion before new data is written to the disk, which slows the process considerably. PCM does not require erase-write cycles. Thus, the extra erase-write activity causes NAND flash performance to degrade faster and, over time, wear out the disk.

      Typically, NAND flash disk life spans range from 5,000 to 10,000 write cycles in consumer disks and up to 100,000 cycles in enterprise-class disks. In contrast, PCM can handle up to an estimated 5 million write cycles.

      Micron, IBM and Intel contend PCM also provides enhanced boot time and simplifies software development, thanks to its inherent speed. It also provides low power consumption and high reliability, Micron said.

      In addition, the design-optimizing shared interface between LPDDR2 and PCM is fully compliant with JEDEC (Joint Electron Devices Engineering Council) industry standards, Micron said.

      Avatar
      Chris Preimesberger
      https://www.eweek.com/author/cpreimesberger/
      Chris J. Preimesberger is Editor-in-Chief of eWEEK and responsible for all the publication's coverage. In his 16 years and more than 5,000 articles at eWEEK, he has distinguished himself in reporting and analysis of the business use of new-gen IT in a variety of sectors, including cloud computing, data center systems, storage, edge systems, security and others. In February 2017 and September 2018, Chris was named among the 250 most influential business journalists in the world (https://richtopia.com/inspirational-people/top-250-business-journalists/) by Richtopia, a UK research firm that used analytics to compile the ranking. He has won several national and regional awards for his work, including a 2011 Folio Award for a profile (https://www.eweek.com/cloud/marc-benioff-trend-seer-and-business-socialist/) of Salesforce founder/CEO Marc Benioff--the only time he has entered the competition. Previously, Chris was a founding editor of both IT Manager's Journal and DevX.com and was managing editor of Software Development magazine. He has been a stringer for the Associated Press since 1983 and resides in Silicon Valley.

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