Intel to Speed Up Chip Redesigns

By John G. Spooner  |  Posted 2006-05-24

Intel to Speed Up Chip Redesigns

PORTLAND, Ore.—Concerns about power consumption are one of the main factors driving chip maker Intel to move more quickly between processor architectures.

Following the arrival of its Core Microarchitecture in June, the chip maker has said it plans to begin delivering a new architecture every two years.

Thus Intel will change out the circuitry that underlies its desktop, notebook and server chips, far more quickly than in the past, when it rolled out new architectures roughly every four years, or sometimes more.

The new cadence has become a necessity, Intel executives said, as the chip maker seeks to meet the goal of boosting its chips performance without increasing their power consumption.

The chip maker aims to tackle that prospect by taking smaller, more frequent steps and also by reusing as much of its previous work as possible, company executives said in a meeting with press and analysts.

The new cadence "is about delivering more performance. If you do it every two years, you can take smaller steps more often as opposed to taking one big step," said Dileep Bhandarkar, an architect in Intels Digital Enterprise Group in Santa Clara, Calif.

"Its much more manageable to do smaller steps every two years versus a big one every four."

Intel is taking the new approach as it comes under increasing competitive pressure from rival Advanced Micro Devices, which has gained market share of late.

Click here to read more about Intels business plans.

The company has accelerated its efforts in the face of that competition, pulling in the launch of its Core Microarchitecture processors in addition to speeding up the cadence at which it will roll out new microarchitectures.

But other challenges have cropped up as well. Chip manufacturing improvements—which in the past have delivered higher performance and lower power—wont yield all the gains Intel wants to meet its goals, the company has also signaled.

Thus, with power consumption being fixed—it can not be allowed to increase, the executives said—the more frequent redesigns become a necessity.

"Were trying to get high performance, but power is no longer a variable like it was before," said Steve Pawlowski, chief technology office for Intels Digital Enterprise Group, in Hillsboro, Ore. "Its a constant."

Intel has shifted between wholly different architectures every several years in the past.

Its NetBurst architecture, which underpins todays Pentium 4 and Xeon chips, emphasized pure speed with less regard to power consumption.

The circuitry behind its Pentium M, on the other hand, emphasized low power and thus wasnt designed to run as fast. But Pentium M chips got more work done per clock.

The Core Microarchitecture, whose derivative chips will begin arriving in June, aimed to take the best elements of both and deliver increased performance, while also lowering power.

Chips like Woodcrest, a dual-core chip that will come in 40 watt, 65 watt and 80 watt variants and run at speeds up to 3GHz, will yield significant power savings, while boosting performance versus existing Xeon processors, the company has said.

Next Page: A new standard.

A New Standard

Given its capabilities, Core Microarchitecture will now become the new standard, and Intel will set upon improving upon it in subsequent generations.

The transition will be "more like a Pentium II to Pentium III kind of thing. Its not something thats so radical that its a complete diversion," Pawlowski said.

"Its really—so when youve got have Core Microarchitecture and you go to Nehalem [Intels next architecture design], you want Nehalem to be similar to this so that youre leveraging off of it and youre adding value there."

Meanwhile, reusing as many elements as possible from Core Microarchitecture will allow Nehalem to be more compatible from generation to generation.

"That way youre not putting stress on the operating system guys—theyre not going to build a generation A and a generation B of the O. Theyre going to build one OS," Pawlowski said.

Intel will also couple its new two-year microarchitecture cadence with its existing two-year manufacturing cycle.

Having rolled out its 65-nanometer manufacturing process in late 2005, the company will begin moving to 45-nanometer manufacturing in 2007.

Read more here about Intels business brand.

The nanometer figures refer to the size of the features inside a chip, which are generally made smaller with each transition, allowing a chip maker to add more transistors.

Generally, increasing transistor counts once meant higher clock speeds. But, in the future, it will allow for increases in the number of processor cores a given chip can contain.

After having delivered its Core Microarchitecture in 2006, it will orchestrate whats called a shrink, moving Core Microarchitecture to 45-nanometers. The shrink is dubbed Penryn.

Then, during 2008, Intel will deliver Nehalem, its next chip architecture, and begin making chips based on it with its 45-naometer manufacturing.

It will begin switching to 32-nanometer chip-making in 2009, executive a Nehalem shrink called Nehamem-C and in 2010 deliver Gesher, yet another new architecture.

Over the period—in which Intel will also be transitioning between dual-core, quad-core and octo-core chips—the company will aim to gain "significant performance increases from generation to generation," Pawlowksi said.

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