Sun Brings Niagara 2 Chip to Open Source

After releasing the multicore, multithreaded chip earlier this year, Sun plans to release the UltraSPARC T2's source code to the open-source community.

Sun Microsystems is releasing the specifications of its new UltraSPARC T2 processor, formally code named Niagara 2, to the open-source community Dec. 12, as part of the company's ongoing effort to build more of a community around its signature chip.

When Sun announced the release of the eight-core UltraSPARC T2 chip in August 2007, company executives said it would move to bring the specification to the open-source community through Sun's OpenSPARC initiative.

The goal of releasing Niagara 2 into the open-source community through the General Public License is to create a larger community around the chip and increase the number of operating systems and applications that can use the processor, said Shrenik Mehta, senior director for Fronted Technologies and the OpenSPARC Program at Sun. In 2005, the company released the specification for the UltraSPARC T1 processor and the designs have been downloaded 6,500 times since then, Mehta said.

"The goal when we released the UltraSPARC specifications in December 2005 was to create a whole new market and grow the ecosystem," Mehta said. "We wanted to make it easy and the easiest and best way to do this is to open it. There is a lot of interest in this technology, so why not share it and grow the pie."

When Sun released the specifications for the first Niagara, Mehta said several other companies took advantage of the design to develop new products. One Italian company, called Simply RISC, used the T1 designs to develop a single-core processor with a wireless interface for mobile devices.

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After taking charge of the company in 2006, CEO Jonathan Schwartz has steadily advocated bringing more and more of the company's products into the open-source community. In addition to its UltraSPARC processors, Sun has also opened up its Solaris operating system through its OpenSolaris program.


To add to this community, Sun also announced that five universities will form the core of a new program called the OpenSPARC Centers of Excellence. The goal of this group is to conduct research and develop courses based on the chips' technology. The five universities that are part of the new program are: the University of California, Santa Cruz; University of Texas, Austin; University of Michigan; University of Illinois, Urbana-Champaign; and Carnegie Mellon University.

Josep Torrellas, a professor of computer science at the University of Illinois, is coordinating the university's OpenSPARC program and said he is eager to begin downloading the millions of lines of source code used to create Niagara 2.

Torrellas specific area of interest is parallel computing, which involves looking at the design and impact of multicore processors, such as the UltraSPARC T2. There are a number of areas that Torrellas and his team intend to look into, including how to make systems more secure on the chip level and how external factors, such as temperature, affect performance.

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Torrellas and his team will also have the chance to see how the instructional threads on each core interact with one another. The UltraSPARC T2 has eight threads on each core for a total of 64 threads.

"This allows us to use a research tool that is different from what we normally use," Torrellas told eWEEK. "This is a state-of-the-art multicore processor design and the benefit for us is to see the internals and then use those specifications as a research vehicle. We also have direct interaction with the computer architecture experts at Sun and this allows us to get deeper into the design and find things we did not know before this program."

When the UltraSPARC T2 specifications are released Tuesday, Mehta said the company plans on releasing most of the source code, including the designs for the logic gate circuitry and the test suites. The one part of the source code that Sun can not release are the algorithms approved by the National Security Agency as part of the chip's cryptographic accelerations units.

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