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IBM announced a chip with brain-inspired non-von Neumann computer architecture that has one million neurons and 256 million synapses.
The chip, known as Systems of Neuromorphic Adaptive Plastic Scalable Electronics, or SyNAPSE, is built on Samsung’s 28nm process technology that has a dense on-chip memory and low-leakage transistors. IBM said it is the first neurosynaptic computer chip to achieve a scale of 1 million programmable neurons, 256 million programmable synapses and 46 billion synaptic operations per second per watt.
And, at 5.4 billion transistors, the production-scale chip is one of the largest CMOS chips ever built, yet while running at biological real time, it consumes only 70mW—orders of magnitude less power than a modern microprocessor, IBM said. As a neurosynaptic supercomputer the size of a postage stamp that runs on the energy equivalent of a hearing-aid battery, SyNAPSE could transform science, technology, business, government and society by enabling vision, auditory and multi-sensory applications.
The long-running project has been funded by the Defense Advanced Research Projects Agency (DARPA). Today’s breakthrough, published in Science in collaboration with Cornell Tech, is a significant step toward bringing cognitive computers to society, IBM said.
“IBM has broken new ground in the field of brain-inspired computers, in terms of a radically new architecture, unprecedented scale, unparalleled power/area/speed efficiency, boundless scalability, and innovative design techniques,” Dr. Dharmendra S. Modha, IBM Fellow and IBM chief scientist for brain-inspired computing at IBM Research, said in a statement. “We foresee new generations of information technology systems—that complement today’s von Neumann machines—powered by an evolving ecosystem of systems, software and services.
“These brain-inspired chips could transform mobility, via sensory and intelligent applications that can fit in the palm of your hand but without the need for WiFi. This achievement underscores IBM’s leadership role at pivotal transformational moments in the history of computing via long-term investment in organic innovation,” he said.
There is a broad disparity between the human brain’s cognitive capability and ultra-low power consumption when compared to today’s computers. To bridge the divide, IBM scientists created an entirely new neuroscience-inspired scalable and efficient computer architecture that breaks path with the prevailing von Neumann architecture used almost universally since 1946.
This second-generation chip is the culmination of almost a decade of research and development, including the initial single core hardware prototype in 2011 and software ecosystem with a new programming language and chip simulator in 2013. With that move, IBM laid the groundwork for the new software model to support all aspects of the programming cycle from design through development, debugging and deployment of apps that mimic the way the brain works.
The new cognitive chip architecture has an on-chip two-dimensional mesh network of 4096 digital, distributed neurosynaptic cores, where each core module integrates memory, computation and communication, and operates in an event-driven, parallel and fault-tolerant fashion. To enable system scaling beyond single-chip boundaries, adjacent chips, when tiled, can seamlessly connect to each other—building a foundation for future neurosynaptic supercomputers. To demonstrate scalability, IBM also revealed a 16-chip system with 16 million programmable neurons and 4 billion programmable synapses.
IBM Unveils SyNAPSE Chip That Mimics the Human Brain
DARPA has funded the project since 2008 with approximately $53M via Phase 0, Phase 1, Phase 2, and Phase 3 of the program. Current collaborators include Cornell Tech and iniLabs.
“It is an astonishing achievement to leverage a process traditionally used for commercially available, low-power mobile devices to deliver a chip that emulates the human brain by processing extreme amounts of sensory information with very little power,” said Shawn Han, vice president of Foundry Marketing at Samsung Electronics, in a statement. “This is a huge architectural breakthrough that is essential as the industry moves toward the next-generation cloud and big-data processing.”
The event-driven circuit elements of the chip used the asynchronous design methodology developed at Cornell Tech and refined with IBM since 2008.
“After years of collaboration with IBM, we are now a step closer to building a computer similar to our brain,” said Professor Rajit Manohar, Cornell Tech.
The combination of cutting-edge process technology, hybrid asynchronous-synchronous design methodology, and new architecture has led to a power density of 20mW/cm2 which is nearly four orders of magnitude less than today’s microprocessors.
The new chip is a component of an end-to-end vertically integrated ecosystem spanning a chip simulator, neuroscience data, supercomputing, neuron specification, programming paradigm, algorithms and applications, and prototype design models. The ecosystem supports all aspects of the programming cycle.
To promote this fundamentally different technological capability, IBM has designed a novel teaching curriculum for universities, customers, partners, and IBM employees.
IBM says this ecosystem signals a shift in moving computation closer to the data, taking in varied kinds of sensory data, analyzing and integrating real-time information in a context-dependent way, and dealing with the ambiguity found in complex, real-world environments.
Meanwhile, looking to the future, IBM is working on integrating multi-sensory neurosynaptic processing into mobile devices constrained by power, volume and speed; integrating novel event-driven sensors with the chip; real-time multimedia cloud services accelerated by neurosynaptic systems; and neurosynaptic supercomputers by tiling multiple chips on a board, creating systems that would eventually scale to one hundred trillion synapses and beyond.
Building on previously demonstrated neurosynaptic cores with on-chip, online learning, IBM said it envisions building learning systems that adapt in real world settings. While today’s hardware is fabricated using a modern CMOS process, the underlying architecture is poised to exploit advances in future memory, 3D integration, logic, and sensor technologies to deliver even lower power, denser package, and faster speed, IBM said.